PCI2050B

ACTIVE

PCI-to-PCI bridge

Product details

Type Bridge Protocols PCIe Applications PCIe Number of channels 2 Speed (max) (Gbps) 0.066 Supply voltage (V) 3.3, 5 Rating Catalog Operating temperature range (°C) -40 to 85
Type Bridge Protocols PCIe Applications PCIe Number of channels 2 Speed (max) (Gbps) 0.066 Supply voltage (V) 3.3, 5 Rating Catalog Operating temperature range (°C) -40 to 85
LQFP (PDV) 208 784 mm² 28 x 28 NFBGA (ZWT) 257 256 mm² 16 x 16
  • Two 32-bit, 66-MHz PCI buses
  • 3.3-V core logic with universal PCI interfaces compatible
    with 3.3-V and 5-V PCI signaling environments
  • Internal two-tier arbitration for up to nine secondary
    bus masters and supports an external secondary bus arbiter
  • Ten secondary PCI clock outputs
  • Independent read and write buffers for each direction
  • Burst data transfers with pipeline architecture to maximize
    data throughput in both directions
  • Supports write combing for enhanced data throughput
  • Up to three delayed transactions in both directions
  • Supports the frame-to-frame delay of only four PCI clocks
    from one bus to another
  • Bus locking propagation
  • Predictable latency per PCI Local Bus Specification
  • Architecture configurable for PCI Bus Power Management
    Interface Specification
  • CompactPCI hot-swap functionality
  • Secondary bus is driven low during reset
  • VGA/palette memory and I/O decoding options
  • Advanced submicron, low-power CMOS technology
  • 208-terminal PDV, 208-terminal PPM, or 257-terminal
    MicroStar BGA™ package

  • Two 32-bit, 66-MHz PCI buses
  • 3.3-V core logic with universal PCI interfaces compatible
    with 3.3-V and 5-V PCI signaling environments
  • Internal two-tier arbitration for up to nine secondary
    bus masters and supports an external secondary bus arbiter
  • Ten secondary PCI clock outputs
  • Independent read and write buffers for each direction
  • Burst data transfers with pipeline architecture to maximize
    data throughput in both directions
  • Supports write combing for enhanced data throughput
  • Up to three delayed transactions in both directions
  • Supports the frame-to-frame delay of only four PCI clocks
    from one bus to another
  • Bus locking propagation
  • Predictable latency per PCI Local Bus Specification
  • Architecture configurable for PCI Bus Power Management
    Interface Specification
  • CompactPCI hot-swap functionality
  • Secondary bus is driven low during reset
  • VGA/palette memory and I/O decoding options
  • Advanced submicron, low-power CMOS technology
  • 208-terminal PDV, 208-terminal PPM, or 257-terminal
    MicroStar BGA™ package

The Texas Instruments PCI2050B PCI-to-PCI bridge provides a high performance connection path between two peripheral component interconnect (PCI) buses operating at a maximum bus frequency of 66-MHz. Transactions occur between masters on one and targets on another PCI bus, and the PCI2050B bridge allows bridged transactions to occur concurrently on both buses. The bridge supports burst mode transfers to maximize data throughput, and the two bus traffic paths through the bridge act independently.

The PCI2050B bridge is compliant with the PCI Local Bus Specification, and can be used to overcome the electrical loading limits of 10 devices per PCI bus and one PCI device per extension slot by creating hierarchical buses. The PCI2050B provides two-tier internal arbitration for up to nine secondary bus masters and may be implemented with an external bus arbiter.

The CompactPCI™ hot-swap extended PCI capability makes the PCI2050B bridge an ideal solution for multifunction compact PCI cards and adapting single function cards to hot-swap compliance.

The PCI2050B bridge is compliant with the PCI-to-PCI Bridge Specification (Revision 1.1). The PCI2050B bridge provides compliance for PCI Bus Power Management Interface Specification (Revision 1.1). The PCI2050B bridge has been designed to lead the industry in power conservation and data throughput. An advanced CMOS process achieves low system power consumption while operating at PCI clock rates up to 66-MHz.

The Texas Instruments PCI2050B PCI-to-PCI bridge provides a high performance connection path between two peripheral component interconnect (PCI) buses operating at a maximum bus frequency of 66-MHz. Transactions occur between masters on one and targets on another PCI bus, and the PCI2050B bridge allows bridged transactions to occur concurrently on both buses. The bridge supports burst mode transfers to maximize data throughput, and the two bus traffic paths through the bridge act independently.

The PCI2050B bridge is compliant with the PCI Local Bus Specification, and can be used to overcome the electrical loading limits of 10 devices per PCI bus and one PCI device per extension slot by creating hierarchical buses. The PCI2050B provides two-tier internal arbitration for up to nine secondary bus masters and may be implemented with an external bus arbiter.

The CompactPCI™ hot-swap extended PCI capability makes the PCI2050B bridge an ideal solution for multifunction compact PCI cards and adapting single function cards to hot-swap compliance.

The PCI2050B bridge is compliant with the PCI-to-PCI Bridge Specification (Revision 1.1). The PCI2050B bridge provides compliance for PCI Bus Power Management Interface Specification (Revision 1.1). The PCI2050B bridge has been designed to lead the industry in power conservation and data throughput. An advanced CMOS process achieves low system power consumption while operating at PCI clock rates up to 66-MHz.

Download View video with transcript Video

Technical documentation

star =Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 5
Type Title Date
* Data sheet PCI-to-PCI Bridge, PCI2050B datasheet (Rev. G) 15 Apr 2013
* Errata PCI2050B Errata (Rev. B) 09 Apr 2009
* User guide HSSC MicroStar BGA Discontinued and Redesigned 08 May 2022
Application note Comparing the PCI2050B to the PCI2050 03 Feb 2006
Application note Difference Between the Intel 21150ac/bc and the PCI2050/2050B (Rev. B) 15 Nov 2005

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Simulation model

PCI2050B IBIS Model

SLLM076.ZIP (15 KB) - IBIS Model
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Simulation tool

TINA-TI — SPICE-based analog simulation program

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
User guide: PDF
Package Pins Download
LQFP (PDV) 208 View options
NFBGA (ZWT) 257 View options

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos