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SN65EL11

ACTIVE

PECL/ECL 1:2 Fanout Buffer

Product details

Rating Catalog Operating temperature range (°C) -40 to 85
Rating Catalog Operating temperature range (°C) -40 to 85
VSSOP (DGK) 8 14.7 mm² (3 mm × 4.9 mm) SOIC (D) 8 29.4 mm² (4.9 mm × 6 mm)
  • 1:2 PECL/ECL Fanout Buffer
  • Operating Range
    • PECL: VCC = 4.2 V to 5.7 V With VEE = 0 V
    • NECL: VCC = 0 V With VEE = -4.2 V to -5.7 V
  • 5-ps Skew Between Outputs
  • Support for Clock Frequencies >2.5 GHz
  • 265-ps Typical Propagation Delay
  • Deterministic Output Value for Open Input Conditions
  • Drop-In Compatible With MC10EL11, MC100EL11
  • Built-In Input Pulldown Resistors
  • Built-In Temperature Compensation
  • APPLICATIONS
    • Data and Clock Transmission Over Backplane
    • Signaling Level Conversion
  • 1:2 PECL/ECL Fanout Buffer
  • Operating Range
    • PECL: VCC = 4.2 V to 5.7 V With VEE = 0 V
    • NECL: VCC = 0 V With VEE = -4.2 V to -5.7 V
  • 5-ps Skew Between Outputs
  • Support for Clock Frequencies >2.5 GHz
  • 265-ps Typical Propagation Delay
  • Deterministic Output Value for Open Input Conditions
  • Drop-In Compatible With MC10EL11, MC100EL11
  • Built-In Input Pulldown Resistors
  • Built-In Temperature Compensation
  • APPLICATIONS
    • Data and Clock Transmission Over Backplane
    • Signaling Level Conversion

The SN65EL11 is a differential 1:2 PECL/ECL fanout buffer. The device includes circuitry to maintain a known logic level when inputs are in an open condition. The SN65EL11 is housed in an industry-standard SOIC-8 package and is also available in a TSSOP-8 package.

The SN65EL11 is a differential 1:2 PECL/ECL fanout buffer. The device includes circuitry to maintain a known logic level when inputs are in an open condition. The SN65EL11 is housed in an industry-standard SOIC-8 package and is also available in a TSSOP-8 package.

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Technical documentation

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Top documentation Type Title Format options Date
* Data sheet 5-V PECL/ECL 1:2 Fanout Buffer datasheet Nov 26, 2008
Application note AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C) Oct 17, 2007

Design & development

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Simulation model

SN65EL11 IBIS Model Version 1.1

SLLM048.ZIP (15 KB) - IBIS model
Supported products & hardware
Package Pins CAD symbols, footprints & 3D models
VSSOP (DGK) 8 Ultra Librarian
SOIC (D) 8 Ultra Librarian

Ordering & quality

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