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Product details

Parameters

Function Buffer Protocols ECL, NECL, PECL Number of transmitters 1 Number of receivers 1 Supply voltage (V) 5 Signaling rate (Mbps) 3500 Input signal ECL, NECL Output signal ECL Rating Catalog Operating temperature range (C) -40 to 85 open-in-new Find other LVDS, M-LVDS & PECL ICs

Package | Pins | Size

SOIC (D) 8 19 mm² 3.91 x 4.9 VSSOP (DGK) 8 15 mm² 3 x 4.9 open-in-new Find other LVDS, M-LVDS & PECL ICs

Features

  • Differential PECL/NECL Receiver
  • Operating Range
    • PECL: VCC = 4.2 V to 5.7 V With VEE = 0 V
    • NECL: VCC = 0 V With VEE = -4.2 V to -5.7 V
  • 250-ps Propagation Delay
  • Support for Clock Frequencies >2 GHz
  • Deterministic Output Value for Open Input Conditions
  • Built-In Temperature Compensation
  • Drop-In Compatible With MC10EL16, MC100EL16
  • Built-In Input Pulldown Resistors
  • APPLICATIONS
    • Data and Clock Transmission Over Backplane
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Description

The SN65EL16 is a differential PECL/ECL receiver with PECL/ECL output. The device includes circuitry to hold Q to a low logic level when the inputs are in an open condition.

The VBB pin is a reference voltage output for the device. When the device is used in the single-ended mode, the unused input should be tied to VBB. This reference voltage can also be used to bias the input when it is ac coupled. When the VBB pin is used, place a 0.01-µF decoupling capacitor between VCC and VBB. Also, limit the sink/source current to <0.5 mA to VBB. Leave VBB open when it is not used.

The SN65EL11 is housed in an industry-standard SOIC-8 package and is also available in a TSSOP-8 package.

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Technical documentation

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Type Title Date
* Data sheet 5.0 V ECL Differential Receiver datasheet Jun. 12, 2008
Application note AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C) Oct. 17, 2007

Design & development

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Design tools & simulation

SIMULATION MODEL Download
SLLM050.ZIP (15 KB) - IBIS Model
SIMULATION TOOL Download
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PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Features
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
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SIMULATION TOOL Download
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TINA-TI TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
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CAD/CAE symbols

Package Pins Download
SOIC (D) 8 View options
VSSOP (DGK) 8 View options

Ordering & quality

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