(1) Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
The SN65LV1023A serializer and SN65LV1224B deserializer comprise a 10-bit serdes chipset designed to transmit and receive serial data over LVDS differential backplanes at equivalent parallel word rates from 10 MHz to 66 MHz. Including overhead, this translates into a serial data rate between 120-Mbps and 792-Mbps payload encoded throughput.
Upon power up, the chipset link can be initialized via a synchronization mode with internally generated SYNC patterns or the deserializer can be allowed to synchronize to random data. By using the synchronization mode, the deserializer establishes lock within specified, shorter time parameters.
The device can be entered into a power-down state when no data transfer is required. Alternatively, a mode is available to place the output pins in the high-impedance state without losing PLL lock.
The SN65LV1023A and SN65LV1224B are characterized for operation over ambient air temperature of -55°C to 125°C.
| Top documentation | Type | Title | Format options | Date |
|---|---|---|---|---|
| * | Data sheet | SN65LV1023A-EP, SN65LV1224B-EP datasheet | Sep 20, 2006 | |
| * | Errata | SN65LV1023A Sync Pattern Generation Logic Error | Jun 26, 2003 | |
| * | VID | SN65LV1023A-EP VID V6206677 | Jun 21, 2016 | |
| * | VID | SN65LV1023A-EP VID V6206677 | Jun 21, 2016 |
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| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| SSOP (DB) | 28 | Ultra Librarian |
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