SN65MLVD207

ACTIVE

Full-duplex M-LVDS transceiver

Product details

Function Transceiver Protocols M-LVDS Number of transmitters 1 Number of receivers 1 Signaling rate (Mbps) 200 Input signal LVTTL, M-LVDS Output signal LVTTL, M-LVDS Rating Catalog Operating temperature range (°C) -40 to 85
Function Transceiver Protocols M-LVDS Number of transmitters 1 Number of receivers 1 Signaling rate (Mbps) 200 Input signal LVTTL, M-LVDS Output signal LVTTL, M-LVDS Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (D) 14 51.9 mm² (8.65 mm × 6 mm)
  • Low-Voltage Differential 30- Line Drivers and Receivers for Signaling Rates(1) Up to 200 Mbps
  • Type-1 Receivers Incorporate 25 mV of Hysteresis
  • Type-2 Receivers Provide an Offset (100 mV) Threshold to Detect Open-Circuit and Idle-Bus Conditions
  • Meets or Exceeds the M-LVDS Standard TIA/EIA-899 for Multipoint Data Interchange
  • Controlled Driver Output Voltage Transition Times for Improved Signal Quality
  • –1 V to 3.4 V Common-Mode Voltage Range Allows Data Transfer With 2 V of Ground Noise
  • Bus Pins High Impedance When Disabled or VCC ≤ 1.5 V
  • 100-Mbps Devices Available (SN65MLVD200A, 202A, 204A, 205A)
  • M-LVDS Bus Power Up/Down Glitch Free
  • APPLICATIONS
    • Low-Power High-Speed Short-Reach
      Alternative to TIA/EIA-485
    • Backplane or Cabled Multipoint Data and Clock Transmission
    • Cellular Base Stations
    • Central-Office Switches
    • Network Switches and Routers

(1) The signaling rate of a line, is the number of voltage transitions that are made per second expressed in the units bps (bits per second).

  • Low-Voltage Differential 30- Line Drivers and Receivers for Signaling Rates(1) Up to 200 Mbps
  • Type-1 Receivers Incorporate 25 mV of Hysteresis
  • Type-2 Receivers Provide an Offset (100 mV) Threshold to Detect Open-Circuit and Idle-Bus Conditions
  • Meets or Exceeds the M-LVDS Standard TIA/EIA-899 for Multipoint Data Interchange
  • Controlled Driver Output Voltage Transition Times for Improved Signal Quality
  • –1 V to 3.4 V Common-Mode Voltage Range Allows Data Transfer With 2 V of Ground Noise
  • Bus Pins High Impedance When Disabled or VCC ≤ 1.5 V
  • 100-Mbps Devices Available (SN65MLVD200A, 202A, 204A, 205A)
  • M-LVDS Bus Power Up/Down Glitch Free
  • APPLICATIONS
    • Low-Power High-Speed Short-Reach
      Alternative to TIA/EIA-485
    • Backplane or Cabled Multipoint Data and Clock Transmission
    • Cellular Base Stations
    • Central-Office Switches
    • Network Switches and Routers

(1) The signaling rate of a line, is the number of voltage transitions that are made per second expressed in the units bps (bits per second).

The SN65MLVD201, 203, 206, and 207 are multipoint-low-voltage differential (M-LVDS) line drivers and receivers, which are optimized to operate at signaling rates up to 200 Mbps. All parts comply with the multipoint low-voltage differential signaling (M-LVDS) standard TIA/EIA-899. These circuits are similar to their TIA/EIA-644 standard compliant LVDS counterparts, with added features to address multipoint applications. The driver output has been designed to support multipoint buses presenting loads as low as 30 , and incorporates controlled transition times to allow for stubs off of the backbone transmission line.

These devices have Type-1 and Type-2 receivers that detect the bus state with as little as 50 mV of differential input voltage over a common-mode voltage range of –1 V to 3.4 V. The Type-1 receivers exhibit 25 mV of differential input voltage hysteresis to prevent output oscillations with slowly changing signals or loss of input. Type-2 receivers include an offset threshold to provide a known output state under open-circuit, idle-bus, and other faults conditions. The devices are characterized for operation from –40°C to 85°C.

The SN65MLVD201, 203, 206, and 207 are multipoint-low-voltage differential (M-LVDS) line drivers and receivers, which are optimized to operate at signaling rates up to 200 Mbps. All parts comply with the multipoint low-voltage differential signaling (M-LVDS) standard TIA/EIA-899. These circuits are similar to their TIA/EIA-644 standard compliant LVDS counterparts, with added features to address multipoint applications. The driver output has been designed to support multipoint buses presenting loads as low as 30 , and incorporates controlled transition times to allow for stubs off of the backbone transmission line.

These devices have Type-1 and Type-2 receivers that detect the bus state with as little as 50 mV of differential input voltage over a common-mode voltage range of –1 V to 3.4 V. The Type-1 receivers exhibit 25 mV of differential input voltage hysteresis to prevent output oscillations with slowly changing signals or loss of input. Type-2 receivers include an offset threshold to provide a known output state under open-circuit, idle-bus, and other faults conditions. The devices are characterized for operation from –40°C to 85°C.

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Technical documentation

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Top documentation Type Title Format options Date
* Data sheet Multipoint-LVDS Line Driver and Receiver datasheet (Rev. C) Jan 7, 2008
Application brief How Far, How Fast Can You Operate MLVDS? Aug 6, 2018
Application note Introduction to M-LVDS (TIA/EIA-899) (Rev. A) Jan 3, 2013
User guide Multipoint-Low Voltage Differential Signaling (M-LVDS) EVM (Rev. B) Apr 5, 2004
Application note M-LVDS Signaling Rate Versus Distance Apr 9, 2003
Application note Interoperability of M-LVDS and BusLVDS Feb 6, 2003
Application note Wired-Logic Signaling with M-LVDS Oct 31, 2002
Application note TIA/EIA-485 and M-LVDS, Power and Speed Comparison Feb 20, 2002

Design & development

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Evaluation board

MLVD20XBEVM — SN65MLVD203B and SN65MLVD204B full-duplex and half-duplex multipoint LVDS (M-LVDS) evaluation mod

User guide: PDF
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Evaluation board

MLVD20XEVM — M-LVDS evaluation module

This evaluation module is for the SN65MLVD203B and SN65MLVD204B, which are M-LVDS transceivers.
The SN65MLVD203B is a full-duplex transceiver, and the SN65MLVD204B is a half-duplex transceiver.
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Simulation model

SN65MLVD207 IBIS Model

SLLC133.ZIP (18 KB) - IBIS model
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SOIC (D) 14 Ultra Librarian

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