The DPHY440 is a 1-lane to 4-lane and clock MIPI DPHY retimer that regenerates the DPHY signaling. The device complies with MIPI DPHY 1.1 standard and can be used in either a MIPI CSI-2 or MIPI DSI application at datarates of up to 1.5Gbps.
The device compensates for PCB, connector, and cable related frequency loss and switching related loss to provide the optimum electrical performance from a CSI-2/DSI source to sink. The DPHY440 DPHY inputs feature configurable equalizers.
The output pins automatically compensate for uneven skew between clock and data lanes received on the inputs ports of the device. The DPHY440 output voltage swing and edge rate can be adjusted by changing the state of the VSADJ_CFG0 pin and ERC pin, respectively.
The DPHY440 is optimized for mobile applications, and contains activity detection circuitry on the DPHY Link interface that can transition into a lower power mode when in ULPS and LP states.
The SN65DPHY440SS is characterized for an industrial temperature range from –40°C to 85°C while SN75DPHY440SS is characterized for commercial temperature range from 0°C to 70°C.
| Top documentation | Type | Title | Format options | Date |
|---|---|---|---|---|
| * | Data sheet | SNx5DPHY440SS MIPI® CSI-2/DSI DPHY Retimer datasheet (Rev. D) | 28 Oct 2024 |
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The DPHY440SSRHREVM is designed to evaluate SN65DPHY440SSRHR device. The EVM has two SAMTEC connectors which provide a means to route DSI or CSI-2 data and clock into and out of the DPHY440.
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| WQFN (RHR) | 28 | Ultra Librarian |
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