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Product details

Parameters

Function Driver Protocols PECL Number of Tx 4 Number of Rx 0 Supply voltage (V) 3.3, 5 Signaling rate (Mbps) 150 Input signal TTL Output signal PECL Rating Catalog Operating temperature range (C) -40 to 85 open-in-new Find other LVDS, M-LVDS & PECL ICs

Package | Pins | Size

SOIC (D) 16 59 mm² 9.9 x 6 SOIC (DW) 16 77 mm² 7.52 x 10.28 open-in-new Find other LVDS, M-LVDS & PECL ICs

Features

  • Functional Replacements for the Agere BDG1A, BPNGA and BDGLA
  • Pin-Equivalent to the General-Trade 26LS31 Device
  • 2.0 ns Maximum Propagation Delays
  • 0.15 ns Output Skew Typical Between ± Pairs
  • Capable of Driving 50- Loads
  • 5.0-V or 3.3-V Supply Operation
  • TB5D1M Includes Surge Protection on
    Differential Outputs
  • TB5D2H No Line Loading When VCC = 0
  • Third State Output Capability
  • -40°C to 85°C Operating Temp Range
  • ESD Protection HBM > 3 kV and CDM > 2 kV
  • Available in Gull-Wing SOIC (JEDEC MS-013, DW) and SOIC (D) Packages
  • APPLICATIONS
    • Digital Data or Clock Transmission Over
      Balanced Transmission Lines

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Description

These quad differential drivers are TTL input to pseudo-ECL differential output used for digital data transmission over balanced transmission lines.

The TB5D1M device is a pin and functional replacement for the Agere systems BDG1A and BPNGA quad differential drivers. The TB5D1M has a built-in lightning protection circuit to absorb large transitions on the transmission lines without destroying the device. When the circuit is powered down it loads the transmission line, because of the protection circuit.

The TB5D2H device is a pin and functional replacement for the Agere systems BDG1A and BDGLA quad differential drivers. Upon power down the TB5D2H output circuit appears as an open circuit and does not load the transmission line.

Both drivers feature a 3-state output with a third-state level of less than 0.1 V.

The packaging options available for these quad differential line drivers include a 16-pin SOIC gull-wing (DW) and a 16-pin SOIC (D) package.

Both drivers are characterized for operation from -40°C to 85°C

The logic inputs of this device include internal pull-up resistors of approximately 40 k that are connected to VCC to ensure a logical high level input if the inputs are open circuited.

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Technical documentation

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Type Title Date
* Datasheet TB5D1M, TB5D2H: Quad Differential PECL Drivers datasheet (Rev. C) Jan. 18, 2008

Design & development

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Design tools & simulation

SIMULATION MODELS Download
SLLC165.ZIP (6 KB) - IBIS Model
SIMULATION MODELS Download
SLLC166.ZIP (6 KB) - IBIS Model
SIMULATION MODELS Download
SLLC167.ZIP (7 KB) - IBIS Model
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SLLC168.ZIP (7 KB) - IBIS Model
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SLLC190.ZIP (9 KB) - IBIS Model
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SLLC191.ZIP (9 KB) - IBIS Model
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SLLC194.ZIP (9 KB) - IBIS Model
SIMULATION MODELS Download
SLLC195.ZIP (9 KB) - IBIS Model
SIMULATION TOOLS Download
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PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
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SIMULATION TOOLS Download
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TINA-TI TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
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CAD/CAE symbols

Package Pins Download
SOIC (D) 16 View options
SOIC (DW) 16 View options

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