Product details

Architecture Current FB Number of channels (#) 1 Total supply voltage (Min) (+5V=5, +/-5V=10) 8 Total supply voltage (Max) (+5V=5, +/-5V=10) 15.8 GBW (Typ) (MHz) 650 BW @ Acl (MHz) 650 Acl, min spec gain (V/V) 3 Slew rate (Typ) (V/us) 3000 Vn at flatband (Typ) (nV/rtHz) 6.6 Vn at 1 kHz (Typ) (nV/rtHz) 22 Iq per channel (Typ) (mA) 34.5 Vos (offset voltage @ 25 C) (Max) (mV) 18 Rail-to-rail No Features Shutdown, Differential to Single-ended conversion Rating Catalog Operating temperature range (C) -40 to 85 CMRR (Typ) (dB) 48 Input bias current (Max) (pA) 4000000 Offset drift (Typ) (uV/C) 58 Output current (Typ) (mA) 95 2nd harmonic (dBc) 66 3rd harmonic (dBc) 68 @ MHz 20
Architecture Current FB Number of channels (#) 1 Total supply voltage (Min) (+5V=5, +/-5V=10) 8 Total supply voltage (Max) (+5V=5, +/-5V=10) 15.8 GBW (Typ) (MHz) 650 BW @ Acl (MHz) 650 Acl, min spec gain (V/V) 3 Slew rate (Typ) (V/us) 3000 Vn at flatband (Typ) (nV/rtHz) 6.6 Vn at 1 kHz (Typ) (nV/rtHz) 22 Iq per channel (Typ) (mA) 34.5 Vos (offset voltage @ 25 C) (Max) (mV) 18 Rail-to-rail No Features Shutdown, Differential to Single-ended conversion Rating Catalog Operating temperature range (C) -40 to 85 CMRR (Typ) (dB) 48 Input bias current (Max) (pA) 4000000 Offset drift (Typ) (uV/C) 58 Output current (Typ) (mA) 95 2nd harmonic (dBc) 66 3rd harmonic (dBc) 68 @ MHz 20
VQFN (RGV) 16 16 mm² 4 x 4
  • Input stage: internal gain of 2 V/V
    • Buffered differential inputs
    • Single-ended low impedance output
    • Full-power bandwidth: 350 MHz (2 VPP)
  • Output stage: gain externally configurable
    • Full-power bandwidth: 270 MHz (5 VPP)
    • Slew rate: 3000 V/µs
    • SPDT input switch and multiplexer
  • Full signal path: input stage and output stage
    • HD2 (20 MHz, 5 VPP to 100 Ω load): –66 dBc
    • HD3 (20 MHz, 5 VPP to 100 Ω load): –68 dBc
    • 10 VPP Output to 100 Ω load using split ±6.5 V supply
    • 12 VPP Output to heavy capacitive loads using single 15 V supply
  • Internal DC reference buffer with low-impedance output
  • Power-supply range:
    • Split supply: ±4 V to ±7.9 V
    • Single supply: 8 V to 15.8 V
  • Input stage: internal gain of 2 V/V
    • Buffered differential inputs
    • Single-ended low impedance output
    • Full-power bandwidth: 350 MHz (2 VPP)
  • Output stage: gain externally configurable
    • Full-power bandwidth: 270 MHz (5 VPP)
    • Slew rate: 3000 V/µs
    • SPDT input switch and multiplexer
  • Full signal path: input stage and output stage
    • HD2 (20 MHz, 5 VPP to 100 Ω load): –66 dBc
    • HD3 (20 MHz, 5 VPP to 100 Ω load): –68 dBc
    • 10 VPP Output to 100 Ω load using split ±6.5 V supply
    • 12 VPP Output to heavy capacitive loads using single 15 V supply
  • Internal DC reference buffer with low-impedance output
  • Power-supply range:
    • Split supply: ±4 V to ±7.9 V
    • Single supply: 8 V to 15.8 V

The THS3215 combines the key signal-chain components required to interface with a complementary-current output, digital-to-analog converter (DAC).

The flexibility provided by this two-stage amplifier system delivers the low distortion, dc-coupled, differential to single-ended signal processing required by a wide range of systems.The input stage buffers the DAC resistive termination, and converts the signal from differential to single-ended with a fixed gain of 2 V/V. The differential to single-ended output is available externally for direct use, and can also be connected through an RLC filter or attenuator to the input of an internal output power stage (OPS). The wideband, current-feedback, output power stage provides all pins externally for flexible gain setting.

An internal 2 × 1 multiplexer (mux) to the output power stage noninverting input provides an easy means to select between the internal differential-to-single-ended stage (D2S) output or an external input.

An optional on-chip midsupply buffer provides a wideband, low-output-impedance source for biasing during single-supply operation through the signal-path stages. This feature provides very simple biasing for single-supply, ac-coupled applications operating up to a maximum 15.8-V supply. An external input to this buffer allows for a dc error-correction loop, or a simple output dc offset feature.

A companion device, the THS3217, provides the same functional features at higher quiescent power and bandwidth. The THS3215 and THS3217 support the emerging high-speed Texas Instruments DACs for AWG applications, such as the DAC38J82.

The THS3215 combines the key signal-chain components required to interface with a complementary-current output, digital-to-analog converter (DAC).

The flexibility provided by this two-stage amplifier system delivers the low distortion, dc-coupled, differential to single-ended signal processing required by a wide range of systems.The input stage buffers the DAC resistive termination, and converts the signal from differential to single-ended with a fixed gain of 2 V/V. The differential to single-ended output is available externally for direct use, and can also be connected through an RLC filter or attenuator to the input of an internal output power stage (OPS). The wideband, current-feedback, output power stage provides all pins externally for flexible gain setting.

An internal 2 × 1 multiplexer (mux) to the output power stage noninverting input provides an easy means to select between the internal differential-to-single-ended stage (D2S) output or an external input.

An optional on-chip midsupply buffer provides a wideband, low-output-impedance source for biasing during single-supply operation through the signal-path stages. This feature provides very simple biasing for single-supply, ac-coupled applications operating up to a maximum 15.8-V supply. An external input to this buffer allows for a dc error-correction loop, or a simple output dc offset feature.

A companion device, the THS3217, provides the same functional features at higher quiescent power and bandwidth. The THS3215 and THS3217 support the emerging high-speed Texas Instruments DACs for AWG applications, such as the DAC38J82.

Download

Technical documentation

star = Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 8
Type Title Date
* Data sheet THS3215 650-MHz, Differential to Single-Ended DAC Output Amplifier datasheet (Rev. C) 18 Jun 2021
Technical article 3 common questions when designing with high-speed amplifiers 17 Jul 2020
Technical article How to reduce distortion in high-voltage, high-frequency signal generation for AWGs 30 Oct 2018
Technical article What are the advantages of using JFET-input amplifiers in high-speed applications? 19 Jun 2018
Technical article Unique active mux capability combines buffer and switch into one solution 10 Oct 2017
E-book The Signal e-book: A compendium of blog posts on op amp design topics 28 Mar 2017
User guide THS3215EVM and THS3217EVM User's Guide (Rev. A) 06 Apr 2016
Application note Noise Analysis for High Speed Op Amps (Rev. A) 17 Jan 2005

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

THS3215EVM — THS3215 Evaluation Module

This evaluation module (EVM) is a demonstration fixture for the THS3215 wideband, differential DAC to single-ended line driver. The EVM provides 50-Ω input and output termination for easy evaluation with common 50-Ω test equipment. The THS3215EVM enables performance evaluation of each (...)
In stock
Limit: 1
Simulation model

THS3215 TINA-TI Spice Model

SBOM978.ZIP (15 KB) - TINA-TI Spice Model
Simulation model

THS3215 TINA-TI Reference Design (Rev. A)

SBOM979A.TSC (62 KB) - TINA-TI Reference Design
Simulation model

THS3215 PSpice Model

SBOMBQ3.ZIP (64 KB) - PSpice Model
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Simulation tool

TINA-TI — SPICE-based analog simulation program

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
Calculation tool

ANALOG-ENGINEER-CALC — Analog engineer's calculator

The Analog Engineer’s Calculator is designed to speed up many of the repetitive calculations that analog circuit design engineers use on a regular basis. This PC-based tool provides a graphical interface with a list of various common calculations ranging from setting op-amp gain with feedback (...)
Calculation tool

VOLT-DIVIDER-CALC — Voltage Divider Determines A Set of Resistors for a Voltage Divider

VOLT-DIVIDER-CALC quickly determines a set of resistors for a voltage divider. This KnowledgeBase Javascript utility can be used to find a set of resistors for a voltage divider to achieve the desired output voltage. This calculator can also be used to design non-inverting attentuation circuits.

(...)

Not available
Package Pins Download
VQFN (RGV) 16 View options

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos