Product details

Number of ADC channels 1 Number of DAC channels (#) 1 Analog inputs 2 Sampling rate (Max) (kHz) 22.05 Rating Military ADC SNR (Typ) (dB) 0 DAC SNR (Typ) (dB) 0
Number of ADC channels 1 Number of DAC channels (#) 1 Analog inputs 2 Sampling rate (Max) (kHz) 22.05 Rating Military ADC SNR (Typ) (dB) 0 DAC SNR (Typ) (dB) 0
LQFP (PT) 48 49 mm² 7 x 7 SOIC (DW) 28 184 mm² 17.9 x 10.3
  • General-purpose analog interface circuit for V.34+ modem and business audio applications
  • 16-bit oversampling sigma-delta ADC and DAC
  • Serial port interface
  • Typical 89-dB SNR (signal-to-noise ratio) for ADC and DAC
  • Typical 90-dB THD (signal to total harmonic distortion) for ADC and DAC
  • Typical 88-dB dynamic range
  • Test mode that includes a digital loopback test and analog loopback test
  • Programmable A/D and D/A conversion rate
  • Programmable input and output gain control
  • Maximum conversion rate: 22.05 kHz
  • Single 5-V power supply voltage or 5-V analog and 3-V digital power supply voltage
  • Power dissipation (PD) of 120 mW rms typical in the operating mode
  • Hardware power-down mode to 7.5 mW
  • Internal reference voltage (Vref)
  • Differential architecture throughout device
  • TLC320AD50C/I can support up to three slave devices; TLC320AD52C can support one slave
  • 2s complement data format
  • ALTDATA terminal provides data monitoring
  • Monitor amplifier to monitor input signals
  • On-chip phase locked loop (PLL)
  • General-purpose analog interface circuit for V.34+ modem and business audio applications
  • 16-bit oversampling sigma-delta ADC and DAC
  • Serial port interface
  • Typical 89-dB SNR (signal-to-noise ratio) for ADC and DAC
  • Typical 90-dB THD (signal to total harmonic distortion) for ADC and DAC
  • Typical 88-dB dynamic range
  • Test mode that includes a digital loopback test and analog loopback test
  • Programmable A/D and D/A conversion rate
  • Programmable input and output gain control
  • Maximum conversion rate: 22.05 kHz
  • Single 5-V power supply voltage or 5-V analog and 3-V digital power supply voltage
  • Power dissipation (PD) of 120 mW rms typical in the operating mode
  • Hardware power-down mode to 7.5 mW
  • Internal reference voltage (Vref)
  • Differential architecture throughout device
  • TLC320AD50C/I can support up to three slave devices; TLC320AD52C can support one slave
  • 2s complement data format
  • ALTDATA terminal provides data monitoring
  • Monitor amplifier to monitor input signals
  • On-chip phase locked loop (PLL)

The TLC320AD50C, TLC320AD50I, and TLC320AD52C provide high-resolution signal conversion from digital-to-analog (D/A) and from analog-to-digital (A/D) using oversampling sigma-delta technology. This device consists of a pair of 16-bit synchronous serial conversion paths (one for each direction) and includes an interpolation filter before the DAC and a decimation filter after the ADC. Other overhead functions on the chip include timing (sample rate, FSD delay) and control (programmable gain amplifier, PLL, communication protocol, etc.). The sigma-delta architecture produces high resolution A/D and D/A conversion at a low system cost.

Programmable functions of this device can be selected through the serial interface. Options include reset, power down, communications protocol, signal sampling rate, gain control, and system test modes (see section 6). The TLC320AD50C and TLC320AD52C are characterized for operation from 0°C to 70°C, and the TLC320AD50I is characterized for operation from \x9640°C to 85°C.

The TLC320AD50C, TLC320AD50I, and TLC320AD52C provide high-resolution signal conversion from digital-to-analog (D/A) and from analog-to-digital (A/D) using oversampling sigma-delta technology. This device consists of a pair of 16-bit synchronous serial conversion paths (one for each direction) and includes an interpolation filter before the DAC and a decimation filter after the ADC. Other overhead functions on the chip include timing (sample rate, FSD delay) and control (programmable gain amplifier, PLL, communication protocol, etc.). The sigma-delta architecture produces high resolution A/D and D/A conversion at a low system cost.

Programmable functions of this device can be selected through the serial interface. Options include reset, power down, communications protocol, signal sampling rate, gain control, and system test modes (see section 6). The TLC320AD50C and TLC320AD52C are characterized for operation from 0°C to 70°C, and the TLC320AD50I is characterized for operation from \x9640°C to 85°C.

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Technical documentation

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Type Title Date
* Data sheet Sigma-Delta Analog Interface Circuits With Master-Slave Function datasheet (Rev. E) 13 Oct 2000
Application note Out-of-Band Noise Measurement Issues for Audio Devices (Rev. A) 31 Dec 2019
Application note Audio Serial Interface Configurations for Audio Codecs (Rev. A) 27 Jun 2019
Application note Using the MSP430 Launchpad as a Standalone I2C Host for Audio Products (Rev. A) 28 Oct 2013
Application note Audio Serial Interface Configurations for Audio Codecs 22 Sep 2010
Application note Solving Enumeration Errors in USB Audio DAC and CODEC Designs 30 Oct 2009
Application note Configuring I2S to Generate BCLK from Codec Devices & WCLK from McBSP Port 08 Jul 2009
EVM User's guide Evaluation Board for the TLC320AD50C DSP Analog Interface Circuit 09 Feb 2000
Application note Comparison of TI Voiceband Codecs for Telephony Applications 08 Dec 1999
Application note Design Guidelines for the TLC320AD50 02 Dec 1999

Design & development

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Evaluation board

TLC320AD50-EVM — TLC320AD50 AIC Evaluation Module

The TLC320AD50 AIC EVM is now available to evaluate the performance of the TLC320AD50 analog interface circuit (AIC), a versatile 16-bit sigma-delta analog front end for modem and business audio applications. The 'AD50 has internal 64x oversampling on the ADC and 256x oversampling on the DAC, and (...)

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PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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LQFP (PT) 48 View options
SOIC (DW) 28 View options

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