74ACT11074

AKTIV

Zweifach-Flipflops (Typ D) mit positiver Flankensteuerung, Clear und Preset

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Datenblatt

document-pdfAcrobat Dual D-Type Positive-Edge-Triggered Flip Flop With Clear And Preset datasheet (Rev. A) (Englisch)

74ACT11074

AKTIV

Jetzt bestellen

Produktdetails

Number of channels

2

Technology family

ACT

Input type

TTL-Compatible CMOS

Output type

Push-Pull

Clock frequency (max) (MHz)

100

IOL (max) (mA)

24

IOH (max) (mA)

-24

Supply current (max) (µA)

40

Features

Balanced outputs, Positive input clamp diode, Very high speed (tpd 5-10ns)

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Number of channels

2

Technology family

ACT

Input type

TTL-Compatible CMOS

Output type

Push-Pull

Clock frequency (max) (MHz)

100

IOL (max) (mA)

24

IOH (max) (mA)

-24

Supply current (max) (µA)

40

Features

Balanced outputs, Positive input clamp diode, Very high speed (tpd 5-10ns)

Operating temperature range (°C)

-40 to 85

Rating

Catalog

SSOP (DB)

14

48.36 mm² (6.2 mm × 7.8 mm)

SOIC (D)

14

51.9 mm² (8.65 mm × 6 mm)

PDIP (N)

14

181.42 mm² (19.3 mm × 9.4 mm)

SOP (NS)

14

79.56 mm² (10.2 mm × 7.8 mm)

Inputs Are TTL-Voltage Compatible
Center-Pin V_CC and GND Configurations to Minimize High-Speed Switching Noise
EPIC^TM (Enhanced-Performance Implanted CMOS) 1-m Process
500-mA Typical Latch-Up Immunity at 125°C
Package Options Include Plastic Small-Outline (D) and Shrink Small-Outline (DB) Packages, and Standard Plastic 300-mil DIPs (N)

EPIC is a trademark of Texas Instruments Incorporated.

Inputs Are TTL-Voltage Compatible
Center-Pin V_CC and GND Configurations to Minimize High-Speed Switching Noise
EPIC^TM (Enhanced-Performance Implanted CMOS) 1-m Process
500-mA Typical Latch-Up Immunity at 125°C
Package Options Include Plastic Small-Outline (D) and Shrink Small-Outline (DB) Packages, and Standard Plastic 300-mil DIPs (N)

EPIC is a trademark of Texas Instruments Incorporated.

This device contains two independent positive-edge-triggered D-type flip-flops. A low level at the preset () or clear () input sets or resets the outputs regardless of the levels of the other inputs. When and are inactive (high), data at the data (D) input meeting the setup-time requirements are transferred to the outputs on the low-to-high transition of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the D input may be changed without affecting the levels at the outputs.

The 74ACT11074 is characterized for operation from -40°C to 85°C.

This device contains two independent positive-edge-triggered D-type flip-flops. A low level at the preset () or clear () input sets or resets the outputs regardless of the levels of the other inputs. When and are inactive (high), data at the data (D) input meeting the setup-time requirements are transferred to the outputs on the low-to-high transition of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the D input may be changed without affecting the levels at the outputs.

The 74ACT11074 is characterized for operation from -40°C to 85°C.

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Top-Dokumentation	Typ	Titel	Format-Optionen	Neueste englische Version herunterladen		Datum
*	Datenblatt	Dual D-Type Positive-Edge-Triggered Flip Flop With Clear And Preset datasheet (Rev. A)			01.04.1996

74ACT11074

Zweifach-Flipflops (Typ D) mit positiver Flankensteuerung, Clear und Preset

74ACT11074

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