ADS54T01

AKTIV

1-kanaliger Rückkopplungs- und Empfänger-IC, 750 MSPS BTS

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Datenblatt

document-pdfAcrobat ADS54T01 Single 12-Bit 750-Msps Receiver and Feedback IC datasheet (Rev. B) (Englisch) PDF | HTML

ADS54T01

AKTIV

Datenblatt

Jetzt bestellen

Produktdetails

Number of input channels

1

Resolution (Bits)

12

Sample rate (max) (Msps)

750

Features

Decimating Filter, Differential Inputs, High Dynamic Range, Nap Mode, Out of Range Indicator, Power Down

Analog input BW (MHz)

1200

Power consumption (typ) (mW)

1200

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Number of input channels

1

Resolution (Bits)

12

Sample rate (max) (Msps)

750

Features

Decimating Filter, Differential Inputs, High Dynamic Range, Nap Mode, Out of Range Indicator, Power Down

Analog input BW (MHz)

1200

Power consumption (typ) (mW)

1200

Operating temperature range (°C)

-40 to 85

Rating

Catalog

NFBGA (ZAY)

196

144 mm² (12 mm × 12 mm)

Single channel
12-bit resolution
Maximum clock rate: 750 Msps
Low swing fullscale input: 1.0 Vpp
Analog input buffer with high impedance input
Input bandwidth (3 dB): > 1.2 GHz
Data output interface: DDR LVDS
196-Pin NFBGA package (12 mm × 12 mm)
Power dissipation: 1.2 W
Performance at f_in = 230 MHz IF
- SNR: 60.7 dBFS
- SFDR: 73 dBc
Performance at f_in = 700 MHz IF
- SNR: 58.6 dBFS
- SFDR: 64 dBc
Receive mode: 2x decimation with low-pass or high-pass filter
Feedback mode: burst mode output for full bandwidth DPD feedback

Single channel
12-bit resolution
Maximum clock rate: 750 Msps
Low swing fullscale input: 1.0 Vpp
Analog input buffer with high impedance input
Input bandwidth (3 dB): > 1.2 GHz
Data output interface: DDR LVDS
196-Pin NFBGA package (12 mm × 12 mm)
Power dissipation: 1.2 W
Performance at f_in = 230 MHz IF
- SNR: 60.7 dBFS
- SFDR: 73 dBc
Performance at f_in = 700 MHz IF
- SNR: 58.6 dBFS
- SFDR: 64 dBc
Receive mode: 2x decimation with low-pass or high-pass filter
Feedback mode: burst mode output for full bandwidth DPD feedback

The ADS54T01 is a high linearity, single channel, 12-bit, 750-Msps analog-to-digital converter (ADC) easing front end filter design for wide bandwidth receivers. The analog input buffer isolates the internal switching of the on-chip track-and-hold from disturbing the signal source as well as providing a high-impedance input.

Two output modes are available for the output data—the data can be decimated by two or the data can be output in burst mode. The burst mode output is designed specifically for DPD feedback applications where high-resolution output data is available for a short period of time. Designed for high SFDR, the ADC has low-noise performance and outstanding spurious-free dynamic range over a large input-frequency range. The device is available in a 196-pin NFBGA package and is specified over the full industrial temperature range (–40°C to 85°C).

The ADS54T01 is a high linearity, single channel, 12-bit, 750-Msps analog-to-digital converter (ADC) easing front end filter design for wide bandwidth receivers. The analog input buffer isolates the internal switching of the on-chip track-and-hold from disturbing the signal source as well as providing a high-impedance input.

Two output modes are available for the output data—the data can be decimated by two or the data can be output in burst mode. The burst mode output is designed specifically for DPD feedback applications where high-resolution output data is available for a short period of time. Designed for high SFDR, the ADC has low-noise performance and outstanding spurious-free dynamic range over a large input-frequency range. The device is available in a 196-pin NFBGA package and is specified over the full industrial temperature range (–40°C to 85°C).

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Technische Dokumentation

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Top-Dokumentation	Typ	Titel	Format-Optionen	Datum
*	Datenblatt	ADS54T01 Single 12-Bit 750-Msps Receiver and Feedback IC datasheet (Rev. B)	PDF \| HTML	01.04.2022
	Anwendungshinweis	Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)		22.05.2015
	Anwendungshinweis	Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)		19.07.2013

Design und Entwicklung

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