CD4019B

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CMOS, Quad-UND/ODER-Schalt-Gatter

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Datenblatt

document-pdfAcrobat CD4019B TYPES datasheet (Rev. C) (Englisch)

CD4019B

AKTIV

Datenblatt

Jetzt bestellen

Produktdetails

Technology family

CD4000

Supply voltage (min) (V)

3

Supply voltage (max) (V)

18

Number of channels

4

Inputs per channel

4

IOL (max) (mA)

6.8

IOH (max) (mA)

-6.8

Input type

Standard CMOS

Output type

Push-Pull

Features

Standard speed (tpd > 50ns)

Data rate (max) (Mbps)

8

Rating

Catalog

Operating temperature range (°C)

-55 to 125

Technology family

CD4000

Supply voltage (min) (V)

3

Supply voltage (max) (V)

18

Number of channels

4

Inputs per channel

4

IOL (max) (mA)

6.8

IOH (max) (mA)

-6.8

Input type

Standard CMOS

Output type

Push-Pull

Features

Standard speed (tpd > 50ns)

Data rate (max) (Mbps)

8

Rating

Catalog

Operating temperature range (°C)

-55 to 125

PDIP (N)

16

181.42 mm² 19.3 x 9.4

SOIC (D)

16

59.4 mm² 9.9 x 6

SOP (NS)

16

79.56 mm² 10.2 x 7.8

TSSOP (PW)

16

32 mm² 5 x 6.4

Medium speed operation……t_PHL = t_PLH = 60 ns (typ.) at C_L = 50 pF, V_DD = 10 V
Standardized, symmetrical output characteristics
100% tested for quiescent current at 20 V
5-V, 10-V, and 15-V parametric ratings
Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
Noise margin (full package-temperature range) =
        1 V at V_DD = 5 V
        2 V at V_DD = 10 V
     2.5 V at V_DD = 15 V
Applications:
- AND-OR select gating
- Shift-right/shift-left registers
- True/complement selection
- AND/OR/Exclusive-OR selection

Medium speed operation……t_PHL = t_PLH = 60 ns (typ.) at C_L = 50 pF, V_DD = 10 V
Standardized, symmetrical output characteristics
100% tested for quiescent current at 20 V
5-V, 10-V, and 15-V parametric ratings
Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
Noise margin (full package-temperature range) =
        1 V at V_DD = 5 V
        2 V at V_DD = 10 V
     2.5 V at V_DD = 15 V
Applications:
- AND-OR select gating
- Shift-right/shift-left registers
- True/complement selection
- AND/OR/Exclusive-OR selection

CD4019B types consist of four AND/OR select gate configurations, each consisting of two 2-input AND gates driving a single-input OR gate. Selection is accomplished by control bits K_a and K_b. In addition to selection of either channel A or channel B information, the control bits can be applied simultaneously to accomplish the logical A + B function.

The CD4019B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

CD4019B types consist of four AND/OR select gate configurations, each consisting of two 2-input AND gates driving a single-input OR gate. Selection is accomplished by control bits K_a and K_b. In addition to selection of either channel A or channel B information, the control bits can be applied simultaneously to accomplish the logical A + B function.

The CD4019B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

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Alle anzeigen 7

	Typ	Titel	Datum
*	Data sheet	CD4019B TYPES datasheet (Rev. C)	15 Okt 2003
	Selection guide	Logic Guide (Rev. AB)	12 Jun 2017
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)	02 Dez 2015
	User guide	LOGIC Pocket Data Book (Rev. B)	16 Jan 2007
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection	08 Jul 2004
	User guide	Signal Switch Data Book (Rev. A)	14 Nov 2003
	Application note	Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics	03 Dez 2001

Design und Entwicklung

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Das 14-24-LOGIC-EVM-Evaluierungsmodul (EVM) ist für die Unterstützung aller Logikgeräte konzipiert, die sich in einem 14-Pin- bis 24-Pin-D-, DW-, DB-, NS-, PW-, DYY- oder DGV-Gehäuse befinden.

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PDIP (N)	16	Optionen anzeigen
SOIC (D)	16	Optionen anzeigen
SOP (NS)	16	Optionen anzeigen
TSSOP (PW)	16	Optionen anzeigen

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CD4019B

CMOS, Quad-UND/ODER-Schalt-Gatter

CD4019B

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