CD74AC175

Name: CD74AC175
Brand: TI
SKU: CD74AC175
Price: 0.239 USD

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Vierfach-Flipflops (Typ D) mit Reset

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Datenblatt

document-pdfAcrobat CD74AC175 Quadruple D-type Flip-Flop with Clear datasheet (Rev. A) (Englisch) PDF | HTML

CD74AC175

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Datenblatt

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Produktdetails

Number of channels

Technology family

Supply voltage (min) (V)

1.5

Supply voltage (max) (V)

5.5

Input type

Standard CMOS

Output type

Push-Pull

Clock frequency (max) (MHz)

100

IOL (max) (mA)

IOH (max) (mA)

-24

Supply current (max) (µA)

160

Features

Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode

Operating temperature range (°C)

-55 to 125

Rating

Catalog

Number of channels

Technology family

Supply voltage (min) (V)

1.5

Supply voltage (max) (V)

5.5

Input type

Standard CMOS

Output type

Push-Pull

Clock frequency (max) (MHz)

100

IOL (max) (mA)

IOH (max) (mA)

-24

Supply current (max) (µA)

160

Features

Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode

Operating temperature range (°C)

-55 to 125

Rating

Catalog

SOIC (D)

59.4 mm² 9.9 x 6

AC types feature 1.5V to 5.5V operation and balanced noise immunity at 30% of the supply voltage
Buffered inputs
Contains four flip-flops with double-rail outputs
Speed of bipolar F, AS, and S, with significantly reduced power consumption
Balanced propagation delays
±24mA output drive current
- Fanout to 15 F devices
SCR-latchup-resistant CMOS process and circuit design
Exceeds 2kV ESD protection per MIL-STD-883, method 3015

AC types feature 1.5V to 5.5V operation and balanced noise immunity at 30% of the supply voltage
Buffered inputs
Contains four flip-flops with double-rail outputs
Speed of bipolar F, AS, and S, with significantly reduced power consumption
Balanced propagation delays
±24mA output drive current
- Fanout to 15 F devices
SCR-latchup-resistant CMOS process and circuit design
Exceeds 2kV ESD protection per MIL-STD-883, method 3015

This positive-edge-triggered D-type flip-flop has a direct clear (CLR) input. The CD74AC175 features complementary outputs from each flip-flop.

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Technische Dokumentation

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Alle anzeigen 14

	Typ	Titel		Datum
*	Data sheet	CD74AC175 Quadruple D-type Flip-Flop with Clear datasheet (Rev. A)	PDF \| HTML	16 Apr 2024
	Application note	Power-Up Behavior of Clocked Devices (Rev. B)	PDF \| HTML	15 Dez 2022
	Application note	Implications of Slow or Floating CMOS Inputs (Rev. E)		26 Jul 2021
	Selection guide	Logic Guide (Rev. AB)		12 Jun 2017
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)		02 Dez 2015
	More literature	HiRel Unitrode Power Management Brochure		07 Jul 2009
	User guide	LOGIC Pocket Data Book (Rev. B)		16 Jan 2007
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection		08 Jul 2004
	Application note	TI IBIS File Creation, Validation, and Distribution Processes		29 Aug 2002
	Application note	CMOS Power Consumption and CPD Calculation (Rev. B)		01 Jun 1997
	Application note	Designing With Logic (Rev. C)		01 Jun 1997
	Application note	Input and Output Characteristics of Digital Integrated Circuits		01 Okt 1996
	Application note	Live Insertion		01 Okt 1996
	Application note	Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc		01 Apr 1996

Design und Entwicklung

Weitere Bedingungen oder erforderliche Ressourcen enthält gegebenenfalls die Detailseite, die Sie durch Klicken auf einen der unten stehenden Titel erreichen.

Evaluierungsplatine

14-24-LOGIC-EVM — Generisches Logikprodukt-Evaluierungsmodul für 14-polige bis 24-polige D-, DB-, DGV-, DW-, DYY-, NS-

Das 14-24-LOGIC-EVM-Evaluierungsmodul (EVM) ist für die Unterstützung aller Logikgeräte konzipiert, die sich in einem 14-Pin- bis 24-Pin-D-, DW-, DB-, NS-, PW-, DYY- oder DGV-Gehäuse befinden.

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