The CD74ACT297 provides a simple, cost-effective solution to high-accuracy, digital, phase-locked-loop applications. This device contains all the necessary circuits, with the exception of the divide-by-N counter, to build first-order phase-locked loops as shown in Figure 1.
Both exclusive-OR phase detectors (XORPDs) and edge-controlled (ECPD) phase detectors are provided for maximum flexibility.
Proper partitioning of the loop function, with many of the building blocks external to the package, makes it easy for the designer to incorporate ripple cancellation or to cascade to higher-order phase-locked loops.
The length of the up/down K counter is digitally programmable according to the K-counter function table. With A, B, C, and D all low, the K counter is disabled. With A high and B, C, and D low, the K counter is only three stages long, which widens the bandwidth, or capture range, and shortens the lock time of the loop. When A, B, C, and D are programmed high, the K counter becomes 17 stages long, which narrows the bandwidth, or capture range, and lengthens the lock time. Real-time control of loop bandwidth by manipulating the A-through-D inputs can maximize the overall performance of the digital phase-locked loop.
This device performs the classic first-order phase-locked-loop function without using analog components. The accuracy of the digital phase-locked loop (DPLL) is not affected by VCC and temperature variations, but depends solely on accuracies of the K clock (K CLK), increment/decrement clock (I/D CLK), and loop propagation delays. The I/D clock frequency and the divide-by-N modulos determine the center frequency of the DPLL. The center frequency is defined by the relationship fc = I/D clock/2N (Hz).
| Typ | Titel | Datum | ||
|---|---|---|---|---|
| * | Data sheet | Digital Phase-Locked Loop datasheet (Rev. D) | 27 Jun 2002 | |
| Application note | Implications of Slow or Floating CMOS Inputs (Rev. E) | 26 Jul 2021 | ||
| Selection guide | Logic Guide (Rev. AB) | 12 Jun 2017 | ||
| Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 02 Dez 2015 | ||
| User guide | LOGIC Pocket Data Book (Rev. B) | 16 Jan 2007 | ||
| Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 08 Jul 2004 | ||
| Application note | Selecting the Right Level Translation Solution (Rev. A) | 22 Jun 2004 | ||
| Application note | TI IBIS File Creation, Validation, and Distribution Processes | 29 Aug 2002 | ||
| Application note | CMOS Power Consumption and CPD Calculation (Rev. B) | 01 Jun 1997 | ||
| Application note | Designing With Logic (Rev. C) | 01 Jun 1997 | ||
| Application note | Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc | 01 Apr 1996 |
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Das 14-24-LOGIC-EVM-Evaluierungsmodul (EVM) ist für die Unterstützung aller Logikgeräte konzipiert, die sich in einem 14-Pin- bis 24-Pin-D-, DW-, DB-, NS-, PW-, DYY- oder DGV-Gehäuse befinden.
| Gehäuse | Pins | Herunterladen |
|---|---|---|
| SOIC (D) | 16 | Optionen anzeigen |
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