Produktdetails

Configuration 8:1 Number of channels 1 Power supply voltage - single (V) 1.8, 2.5, 3.3, 5 Power supply voltage - dual (V) +/-2.5, +/-5 Protocols Analog Ron (typ) (Ω) 40 CON (typ) (pF) 25 ON-state leakage current (max) (µA) 1 Supply current (typ) (µA) 8 Bandwidth (MHz) 180 Operating temperature range (°C) -55 to 125 Features Break-before-make Input/output continuous current (max) (mA) 25 Rating HiRel Enhanced Product Drain supply voltage (max) (V) 6 Supply voltage (max) (V) 10 Negative rail supply voltage (max) (V) 0
Configuration 8:1 Number of channels 1 Power supply voltage - single (V) 1.8, 2.5, 3.3, 5 Power supply voltage - dual (V) +/-2.5, +/-5 Protocols Analog Ron (typ) (Ω) 40 CON (typ) (pF) 25 ON-state leakage current (max) (µA) 1 Supply current (typ) (µA) 8 Bandwidth (MHz) 180 Operating temperature range (°C) -55 to 125 Features Break-before-make Input/output continuous current (max) (mA) 25 Rating HiRel Enhanced Product Drain supply voltage (max) (V) 6 Supply voltage (max) (V) 10 Negative rail supply voltage (max) (V) 0
SOIC (D) 16 59.4 mm² 9.9 x 6
  • Controlled Baseline
    • One Assembly and Test Site, One Fabrication Site
  • Extended Temperature Performance of –55°C to 125°C
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product Change Notification
  • Qualification Pedigree(1)
  • Wide Analog Input Voltage Range of ±5 V Max
  • Low ON-Resistance
    • 70 Ω Typical (VCC – VEE = 4.5 V)
    • 40 Ω Typical (VCC – VEE = 9 V)
  • Low Crosstalk Between Switches
  • Fast Switching and Propagation Speeds
  • Break-Before-Make Switching
  • Operation Control Voltage = 2 V to 6 V
  • Switch Voltage = 0 V to 10 V
  • High Noise Immunity NIL = 30%, NIH = 30% of VCC,
    VCC = 5 V
  • Controlled Baseline
    • One Assembly and Test Site, One Fabrication Site
  • Extended Temperature Performance of –55°C to 125°C
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product Change Notification
  • Qualification Pedigree(1)
  • Wide Analog Input Voltage Range of ±5 V Max
  • Low ON-Resistance
    • 70 Ω Typical (VCC – VEE = 4.5 V)
    • 40 Ω Typical (VCC – VEE = 9 V)
  • Low Crosstalk Between Switches
  • Fast Switching and Propagation Speeds
  • Break-Before-Make Switching
  • Operation Control Voltage = 2 V to 6 V
  • Switch Voltage = 0 V to 10 V
  • High Noise Immunity NIL = 30%, NIH = 30% of VCC,
    VCC = 5 V

The CD74HC4051-EP is a digitally controlled analog switch that uses silicon gate CMOS technology to achieve operating speeds similar to LSTTL, with the low power consumption of standard CMOS integrated circuits.

This analog multiplexer and demultiplexer controls analog voltages that may vary across the voltage supply range (that is, VCC to VEE). These bidirectional switches allow the use of any analog input as an output and vice versa. The switches have low ON-resistance and low OFF leakages. In addition, the device has an enable control (E) that, when high, disables all switches to their OFF state.

The CD74HC4051-EP is a digitally controlled analog switch that uses silicon gate CMOS technology to achieve operating speeds similar to LSTTL, with the low power consumption of standard CMOS integrated circuits.

This analog multiplexer and demultiplexer controls analog voltages that may vary across the voltage supply range (that is, VCC to VEE). These bidirectional switches allow the use of any analog input as an output and vice versa. The switches have low ON-resistance and low OFF leakages. In addition, the device has an enable control (E) that, when high, disables all switches to their OFF state.

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Technische Dokumentation

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Typ Titel Datum
* Data sheet CD74HC4051-EP Analog Multiplexer and Demultiplexer datasheet (Rev. A) PDF | HTML 03 Sep 2014
* VID CD74HC4051-EP VID V6203606 21 Jun 2016
* Radiation & reliability report CD74HC4051MM96EP Reliability Report 25 Aug 2011
Application note Selecting the Correct Texas Instruments Signal Switch (Rev. E) PDF | HTML 02 Jun 2022
Application note Multiplexers and Signal Switches Glossary (Rev. B) PDF | HTML 01 Dez 2021
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dez 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Okt 1996
Application note Live Insertion 01 Okt 1996
Application note SN54/74HCT CMOS Logic Family Applications and Restrictions 01 Mai 1996
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 01 Apr 1996

Design und Entwicklung

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Gehäuse Pins CAD-Symbole, Footprints und 3D-Modelle
SOIC (D) 16 Ultra Librarian

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  • REACH
  • Bausteinkennzeichnung
  • Blei-Finish/Ball-Material
  • MSL-Rating / Spitzenrückfluss
  • MTBF-/FIT-Schätzungen
  • Materialinhalt
  • Qualifikationszusammenfassung
  • Kontinuierliches Zuverlässigkeitsmonitoring
Beinhaltete Information:
  • Werksstandort
  • Montagestandort

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