CD74HCT273

Name: CD74HCT273
Brand: TI
SKU: CD74HCT273
Price: 0.363 USD

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Achtfacher Highspeed-CMOS-Logik-D-Flipflop mit Reset

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Datenblatt

document-pdfAcrobat CDx4HC(T)273 High-Speed CMOS Logic Octal D-Type Flip-Flop with Reset datasheet (Rev. D) (Englisch) PDF | HTML

CD74HCT273

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Datenblatt

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Produktdetails

Number of channels

8

Technology family

HCT

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Input type

TTL-Compatible CMOS

Output type

Push-Pull

Clock frequency (max) (MHz)

16

IOL (max) (mA)

4

IOH (max) (mA)

-4

Supply current (max) (µA)

160

Features

Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode

Operating temperature range (°C)

-55 to 125

Rating

Catalog

Number of channels

8

Technology family

HCT

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Input type

TTL-Compatible CMOS

Output type

Push-Pull

Clock frequency (max) (MHz)

16

IOL (max) (mA)

4

IOH (max) (mA)

-4

Supply current (max) (µA)

160

Features

Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode

Operating temperature range (°C)

-55 to 125

Rating

Catalog

PDIP (N)

20

228.702 mm² 24.33 x 9.4

SOIC (DW)

20

131.84 mm² 12.8 x 10.3

Common clock and asynchronous controller reset
Positive edge triggering
Buffered inputs
Fanout (over temperature range)
- Standard outputs: 10 LSTTL loads
- Bus driver outputs: 15 LSTTL loads
Wide operating temperature range: –55℃ to 125℃
Balanced propagation delay and transition times
Significant power reduction compared to LSTTL Logic ICs
HC types:
- 2V to 6V operation
- High noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
HCT types:
- 4.5V to 5.5V operation
- Direct LSTTL input logic compatibility, VIL = 0.8V (maximum), VIH = 2V (minimum)
- CMOS input compatibility, II ≤ 1µA at VOL,VOH

Common clock and asynchronous controller reset
Positive edge triggering
Buffered inputs
Fanout (over temperature range)
- Standard outputs: 10 LSTTL loads
- Bus driver outputs: 15 LSTTL loads
Wide operating temperature range: –55℃ to 125℃
Balanced propagation delay and transition times
Significant power reduction compared to LSTTL Logic ICs
HC types:
- 2V to 6V operation
- High noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
HCT types:
- 4.5V to 5.5V operation
- Direct LSTTL input logic compatibility, VIL = 0.8V (maximum), VIH = 2V (minimum)
- CMOS input compatibility, II ≤ 1µA at VOL,VOH

The CD54HC273, CD74HC273, CD54HCT273, and CD74HCT273 high speed octal D-Type flip-flops with a direct clear input are manufactured with silicongate CMOS technology. The devices possess the low power consumption of standard CMOS integrated circuits.

Information at the D input transfers to the Q outputs on the positive-going edge of the clock pulse. All eight flip-flops are controlled by a common clock (CLK) and a common reset (/CLR). Resetting is accomplished by a low voltage level independent of the clock. All eight Q outputs reset to a logic 0.

The CD54HC273, CD74HC273, CD54HCT273, and CD74HCT273 high speed octal D-Type flip-flops with a direct clear input are manufactured with silicongate CMOS technology. The devices possess the low power consumption of standard CMOS integrated circuits.

Information at the D input transfers to the Q outputs on the positive-going edge of the clock pulse. All eight flip-flops are controlled by a common clock (CLK) and a common reset (/CLR). Resetting is accomplished by a low voltage level independent of the clock. All eight Q outputs reset to a logic 0.

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	Typ	Titel		Datum
*	Data sheet	CDx4HC(T)273 High-Speed CMOS Logic Octal D-Type Flip-Flop with Reset datasheet (Rev. D)	PDF \| HTML	28 Okt 2025
	Selection guide	Logic Guide (Rev. AC)	PDF \| HTML	13 Nov 2025
	Application note	Power-Up Behavior of Clocked Devices (Rev. B)	PDF \| HTML	15 Dez 2022
	Application note	Implications of Slow or Floating CMOS Inputs (Rev. E)		26 Jul 2021
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)		02 Dez 2015
	User guide	LOGIC Pocket Data Book (Rev. B)		16 Jan 2007
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection		08 Jul 2004
	User guide	Signal Switch Data Book (Rev. A)		14 Nov 2003
	Application note	TI IBIS File Creation, Validation, and Distribution Processes		29 Aug 2002
	Application note	CMOS Power Consumption and CPD Calculation (Rev. B)		01 Jun 1997
	Application note	Designing With Logic (Rev. C)		01 Jun 1997
	Application note	SN54/74HCT CMOS Logic Family Applications and Restrictions		01 Mai 1996
	Application note	Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc		01 Apr 1996

Design und Entwicklung

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Evaluierungsplatine

14-24-LOGIC-EVM — Generisches Logikprodukt-Evaluierungsmodul für 14-polige bis 24-polige D-, DB-, DGV-, DW-, DYY-, NS-

Das 14-24-LOGIC-EVM-Evaluierungsmodul (EVM) ist für die Unterstützung aller Logikgeräte konzipiert, die sich in einem 14-Pin- bis 24-Pin-D-, DW-, DB-, NS-, PW-, DYY- oder DGV-Gehäuse befinden.

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Gehäuse	Pins	CAD-Symbole, Footprints und 3D-Modelle
PDIP (N)	20	Ultra Librarian
SOIC (DW)	20	Ultra Librarian

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CD74HCT273

Achtfacher Highspeed-CMOS-Logik-D-Flipflop mit Reset

CD74HCT273

Produktdetails

Technische Dokumentation

Design und Entwicklung

14-24-LOGIC-EVM — Generisches Logikprodukt-Evaluierungsmodul für 14-polige bis 24-polige D-, DB-, DGV-, DW-, DYY-, NS-

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