CY54FCT373T

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Transparente Achtfach-Latches (Typ D), mit Tri-State-Ausgängen

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Datenblatt

document-pdfAcrobat 8-Bit Latches datasheet (Rev. B) (Englisch)

Benutzerhandbücher

document-pdfAcrobat
CYFCT Parameter Measurement Information (Englisch)

CY54FCT373T

AKTIV

Datenblatt

Jetzt bestellen

Produktdetails

Number of channels

8

Technology family

FCT

Operating temperature range (°C)

-55 to 125

Rating

Military

Number of channels

8

Technology family

FCT

Operating temperature range (°C)

-55 to 125

Rating

Military

CDIP (J)

20

167.464 mm² (— mm × — mm)

LCCC (FK)

20

79.0321 mm² (— mm × — mm)

Function and Pinout Compatible With FCT and F Logic
Reduced V_OH (Typically = 3.3 V) Versions of Equivalent FCT Functions
Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
I_off Supports Partial-Power-Down Mode Operation
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
Matched Rise and Fall Times
Fully Compatible With TTL Input and Output Logic Levels
3-State Outputs
CY54FCT373T
- 32-mA Output Sink Current
- 12-mA Output Source Current
CY74FCT373T
- 64-mA Output Sink Current
- 32-mA Output Source Current

Function and Pinout Compatible With FCT and F Logic
Reduced V_OH (Typically = 3.3 V) Versions of Equivalent FCT Functions
Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
I_off Supports Partial-Power-Down Mode Operation
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
Matched Rise and Fall Times
Fully Compatible With TTL Input and Output Logic Levels
3-State Outputs
CY54FCT373T
- 32-mA Output Sink Current
- 12-mA Output Source Current
CY74FCT373T
- 64-mA Output Sink Current
- 32-mA Output Source Current

The \x92FCT373T devices consist of eight latches with 3-state outputs for bus-organized applications. When the latch-enable (LE) input is high, the flip-flops appear transparent to the data. Data that meets the required setup times are latched when LE transitions from high to low. Data appears on the bus when the output-enable (OE\) input is low. When OE\ is high, the bus output is in the high-impedance state. In this mode, data can be entered into the latches.

These devices are fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The \x92FCT373T devices consist of eight latches with 3-state outputs for bus-organized applications. When the latch-enable (LE) input is high, the flip-flops appear transparent to the data. Data that meets the required setup times are latched when LE transitions from high to low. Data appears on the bus when the output-enable (OE\) input is low. When OE\ is high, the bus output is in the high-impedance state. In this mode, data can be entered into the latches.

These devices are fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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Top-Dokumentation	Typ	Titel	Datum
*	Datenblatt	8-Bit Latches datasheet (Rev. B)	20.08.2001
*	Benutzerhandbuch	CYFCT Parameter Measurement Information	02.04.2001
*	SMD	CY54FCT373T SMD 5962-92217	21.06.2016

CY54FCT373T

Transparente Achtfach-Latches (Typ D), mit Tri-State-Ausgängen

CY54FCT373T

Produktdetails

Technische Dokumentation

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