SN54HC138

Name: SN54HC138
Brand: TI
SKU: SN54HC138
Price: 24.78 USD

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Datenblatt

document-pdfAcrobat SNx4HC138 3-Line To 8-Line Decoders/Demultiplexers datasheet (Rev. G) (Englisch) PDF | HTML

SN54HC138

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Datenblatt

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Produktdetails

Technology family

HC

Number of channels

1

Operating temperature range (°C)

-55 to 125

Rating

Military

Supply current (max) (µA)

160

Technology family

HC

Number of channels

1

Operating temperature range (°C)

-55 to 125

Rating

Military

Supply current (max) (µA)

160

CDIP (J)

16

135.3552 mm² 19.56 x 6.92

CFP (W)

16

69.319 mm² 10.3 x 6.73

LCCC (FK)

20

79.0321 mm² 8.89 x 8.89

Targeted Specifically for High-Speed Memory Decoders and Data-Transmission Systems
Wide Operating Voltage Range (2 V to 6 V)
Outputs Can Drive Up To 10 LSTTL Loads
Low Power Consumption, 80-µA Maximum I_CC
Typical t_pd = 15 ns
±4-mA Output Drive at 5 V
Low Input Current of 1-µA Maximum
Active Low Outputs ( Selected Output is Low)
Incorporate Three Enable Inputs to Simplify Cascading or Data Reception

Targeted Specifically for High-Speed Memory Decoders and Data-Transmission Systems
Wide Operating Voltage Range (2 V to 6 V)
Outputs Can Drive Up To 10 LSTTL Loads
Low Power Consumption, 80-µA Maximum I_CC
Typical t_pd = 15 ns
±4-mA Output Drive at 5 V
Low Input Current of 1-µA Maximum
Active Low Outputs ( Selected Output is Low)
Incorporate Three Enable Inputs to Simplify Cascading or Data Reception

The SNx4HC138 devices are designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories using a fast enable circuit, the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.

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	Typ	Titel		Datum
*	Data sheet	SNx4HC138 3-Line To 8-Line Decoders/Demultiplexers datasheet (Rev. G)	PDF \| HTML	08 Okt 2021
*	SMD	SN54HC138 SMD 84062012A		21 Jun 2016
	Application note	Implications of Slow or Floating CMOS Inputs (Rev. E)		26 Jul 2021
	Selection guide	Logic Guide (Rev. AB)		12 Jun 2017
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)		02 Dez 2015
	User guide	LOGIC Pocket Data Book (Rev. B)		16 Jan 2007
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection		08 Jul 2004
	User guide	Signal Switch Data Book (Rev. A)		14 Nov 2003
	Application note	TI IBIS File Creation, Validation, and Distribution Processes		29 Aug 2002
	Application note	CMOS Power Consumption and CPD Calculation (Rev. B)		01 Jun 1997
	Application note	Designing With Logic (Rev. C)		01 Jun 1997
	Application note	Input and Output Characteristics of Digital Integrated Circuits		01 Okt 1996
	Application note	Live Insertion		01 Okt 1996
	Application note	SN54/74HCT CMOS Logic Family Applications and Restrictions		01 Mai 1996
	Application note	Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc		01 Apr 1996

Design und Entwicklung

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Gehäuse	Pins	Herunterladen
CDIP (J)	16	Optionen anzeigen
CFP (W)	16	Optionen anzeigen
LCCC (FK)	20	Optionen anzeigen

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SN54HC138

Decoder/Demultiplexer, 3 Leitungen auf 8 Leitungen

SN54HC138

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Design und Entwicklung

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