These devices contain two independent D-type positive-edge-triggered flip-flops. A low level at the preset or clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the D input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the D input may be changed without affecting the levels at the outputs.
The SN54' family is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74' family is characterized for operation from 0°C to 70°C.
| Typ | Titel | Datum | ||
|---|---|---|---|---|
| * | Data sheet | Dual D-Type Positive-Edge -Triggered Flip-Flops With Preset And Clear datasheet | 01 Mär 1988 | |
| Application note | Power-Up Behavior of Clocked Devices (Rev. B) | PDF | HTML | 15 Dez 2022 | |
| Selection guide | Logic Guide (Rev. AB) | 12 Jun 2017 | ||
| Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 02 Dez 2015 | ||
| User guide | LOGIC Pocket Data Book (Rev. B) | 16 Jan 2007 | ||
| Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 08 Jul 2004 | ||
| Application note | Designing With Logic (Rev. C) | 01 Jun 1997 | ||
| Application note | Input and Output Characteristics of Digital Integrated Circuits | 01 Okt 1996 | ||
| Application note | Live Insertion | 01 Okt 1996 |
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| Gehäuse | Pins | Herunterladen |
|---|---|---|
| CDIP (J) | 14 | Optionen anzeigen |
| CFP (W) | 14 | Optionen anzeigen |
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