These 10-bit edge-triggered D-type flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. These devices are particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers.
On the positive transition of the clock (CLK) input, the Q outputs are true to the data (D) input.
A buffered output-enable (
) input can place the ten outputs in either a normal
logic state (high or low logic levels) or a high-impedance state. The
outputs also are in the high-impedance state during power-up and
power-down conditions. The outputs remain in the high-impedance state
while the device is powered down. In the high-impedance state, the
outputs neither load nor drive the bus lines significantly. The
high-impedance state and increased drive provide the capability to
drive bus lines without interface or pullup components.
does not affect
the internal operation of the flip-flops. Old data can be retained or
new data can be entered while the outputs are in the high-impedance
state.
The SN54ALS29821 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS29821 is characterized for operation from 0°C to 70°C.
| Typ | Titel | Datum | ||
|---|---|---|---|---|
| * | Data sheet | 10-Bit Bus Interface Flip-Flops With 3-State Outputs datasheet (Rev. B) | 01 Jan 1995 | |
| Application note | Power-Up Behavior of Clocked Devices (Rev. B) | PDF | HTML | 15 Dez 2022 | |
| Selection guide | Logic Guide (Rev. AB) | 12 Jun 2017 | ||
| Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 02 Dez 2015 | ||
| User guide | LOGIC Pocket Data Book (Rev. B) | 16 Jan 2007 | ||
| Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 08 Jul 2004 | ||
| Application note | TI IBIS File Creation, Validation, and Distribution Processes | 29 Aug 2002 | ||
| Application note | Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) | 01 Aug 1997 | ||
| Application note | Designing With Logic (Rev. C) | 01 Jun 1997 | ||
| Application note | Input and Output Characteristics of Digital Integrated Circuits | 01 Okt 1996 | ||
| Application note | Live Insertion | 01 Okt 1996 | ||
| Application note | Advanced Schottky (ALS and AS) Logic Families | 01 Aug 1995 |
Weitere Bedingungen oder erforderliche Ressourcen enthält gegebenenfalls die Detailseite, die Sie durch Klicken auf einen der unten stehenden Titel erreichen.
Das 14-24-LOGIC-EVM-Evaluierungsmodul (EVM) ist für die Unterstützung aller Logikgeräte konzipiert, die sich in einem 14-Pin- bis 24-Pin-D-, DW-, DB-, NS-, PW-, DYY- oder DGV-Gehäuse befinden.
| Gehäuse | Pins | Herunterladen |
|---|---|---|
| SOIC (DW) | 24 | Optionen anzeigen |
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