SN74ALS569A

AKTIV

Synchrone Aufwärts-/Abwärts-Binärzähler mit 4 Bit und Tri-State-Ausgängen

Produktdetails

Function Counter Bits (#) 4 Technology family ALS Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type Bipolar Output type 3-State Features High speed (tpd 10-50ns) Operating temperature range (°C) 0 to 70 Rating Catalog
Function Counter Bits (#) 4 Technology family ALS Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type Bipolar Output type 3-State Features High speed (tpd 10-50ns) Operating temperature range (°C) 0 to 70 Rating Catalog
PDIP (N) 20 228.702 mm² 24.33 x 9.4 SOIC (DW) 20 131.84 mm² 12.8 x 10.3
  • 3-State Q Outputs Drive Bus Lines Directly
  • Counter Operation Independent of 3-State Output
  • Fully Synchronous Clear, Count, and Load
  • Asynchronous Clear Is Also Provided
  • Fully Cascadable
  • Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs

 

  • 3-State Q Outputs Drive Bus Lines Directly
  • Counter Operation Independent of 3-State Output
  • Fully Synchronous Clear, Count, and Load
  • Asynchronous Clear Is Also Provided
  • Fully Cascadable
  • Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs

 

The SN74ALS568A decade counter and ´ALS569A binary counters are programmable, count up or down, and offer both synchronous and asynchronous clearing. All synchronous functions are executed on the positive-going edge of the clock (CLK) input.

The clear function is initiated by applying a low level to either asynchronous clear (ACLR\) or synchronous clear (SCLR\). Asynchronous (direct) clearing overrides all other functions of the device, while synchronous clearing overrides only the other synchronous functions. Data is loaded from the A, B, C, and D inputs by holding load () low during a positive-going clock transition. The counting function is enabled only when enable P (ENP\) and enable T (ENT\) are low and ACLR\, SCLR\, and are high. The up/down (U/D\) input controls the direction of the count. These counters count up when U/D\ is high and count down when U/D\ is low.

A high level at the output-enable () input forces the Q outputs into the high-impedance state, and a low level enables those outputs. Counting is independent of . ENT\ is fed forward to enable the ripple-carry output (RCO\) to produce a low-level pulse while the count is zero (all Q outputs low) when counting down or maximum (9 or 15) when counting up. The clocked carry output (CCO\) produces a low-level pulse for a duration equal to that of the low level of the clock when is low and the counter is enabled (both ENP\ and ENT\ are low); otherwise, CCO\ is high. CCO\ does not have the glitches commonly associated with a ripple-carry output. Cascading is normally accomplished by connecting or CCO\ of the first counter to ENT\ of the next counter. However, for very high-speed counting, should be used for cascading since CCO\ does not become active until the clock returns to the low level.

The SN54ALS569A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS568A and SN74ALS569A are characterized for operation from 0°C to 70°C.

 

 

The SN74ALS568A decade counter and ´ALS569A binary counters are programmable, count up or down, and offer both synchronous and asynchronous clearing. All synchronous functions are executed on the positive-going edge of the clock (CLK) input.

The clear function is initiated by applying a low level to either asynchronous clear (ACLR\) or synchronous clear (SCLR\). Asynchronous (direct) clearing overrides all other functions of the device, while synchronous clearing overrides only the other synchronous functions. Data is loaded from the A, B, C, and D inputs by holding load () low during a positive-going clock transition. The counting function is enabled only when enable P (ENP\) and enable T (ENT\) are low and ACLR\, SCLR\, and are high. The up/down (U/D\) input controls the direction of the count. These counters count up when U/D\ is high and count down when U/D\ is low.

A high level at the output-enable () input forces the Q outputs into the high-impedance state, and a low level enables those outputs. Counting is independent of . ENT\ is fed forward to enable the ripple-carry output (RCO\) to produce a low-level pulse while the count is zero (all Q outputs low) when counting down or maximum (9 or 15) when counting up. The clocked carry output (CCO\) produces a low-level pulse for a duration equal to that of the low level of the clock when is low and the counter is enabled (both ENP\ and ENT\ are low); otherwise, CCO\ is high. CCO\ does not have the glitches commonly associated with a ripple-carry output. Cascading is normally accomplished by connecting or CCO\ of the first counter to ENT\ of the next counter. However, for very high-speed counting, should be used for cascading since CCO\ does not become active until the clock returns to the low level.

The SN54ALS569A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS568A and SN74ALS569A are characterized for operation from 0°C to 70°C.

 

 

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Typ Titel Datum
* Data sheet Synchronous 4-Bit Up/Down Decade And Binary Counters With 3-State Outputs datasheet (Rev. A) 01 Jan 1995
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dez 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 Aug 1997
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Okt 1996
Application note Live Insertion 01 Okt 1996
Application note Advanced Schottky (ALS and AS) Logic Families 01 Aug 1995

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