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SN74ALVC164245

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Pegelverschiebungs-Transceiver mit 16 Bit, 2,5 V bis 3,3 V/3,3 V bis 5 V. mit Tri-State-Ausgängen

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Datenblatt

SN74ALVC164245

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Produktdetails

Bits (#) 16 Data rate (max) (Mbps) 300 Topology Push-Pull Direction control (typ) Direction-controlled Vin (min) (V) 2.5 Vin (max) (V) 3.3 Vout (min) (V) 3.3 Vout (max) (V) 5 Applications GPIO Features Output enable, Very high speed Technology family ALVC Supply current (max) (mA) 0.04 Rating Catalog Operating temperature range (°C) -40 to 85
Bits (#) 16 Data rate (max) (Mbps) 300 Topology Push-Pull Direction control (typ) Direction-controlled Vin (min) (V) 2.5 Vin (max) (V) 3.3 Vout (min) (V) 3.3 Vout (max) (V) 5 Applications GPIO Features Output enable, Very high speed Technology family ALVC Supply current (max) (mA) 0.04 Rating Catalog Operating temperature range (°C) -40 to 85
SSOP (DL) 48 164.358 mm² (15.88 mm × 10.35 mm) TSSOP (DGG) 48 101.25 mm² (12.5 mm × 8.1 mm)
  • Member of the Texas Instruments Widebus™ Family
  • Maximum tpd of 5.8 ns at 3.3 V
  • ±24-mA Output Drive at 3.3 V
  • Control Inputs VIH/VIL Levels Are Referenced to VCCA Voltage
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • APPLICATIONS
    • Electronic Points of Sale
    • Printers and Other Peripherals
    • Motor Drives
    • Wireless and Telecom Infrastructures
    • Wearable Health and Fitness Devices

All other trademarks are the property of their respective owners
  • Member of the Texas Instruments Widebus™ Family
  • Maximum tpd of 5.8 ns at 3.3 V
  • ±24-mA Output Drive at 3.3 V
  • Control Inputs VIH/VIL Levels Are Referenced to VCCA Voltage
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • APPLICATIONS
    • Electronic Points of Sale
    • Printers and Other Peripherals
    • Motor Drives
    • Wireless and Telecom Infrastructures
    • Wearable Health and Fitness Devices

All other trademarks are the property of their respective owners

This 16-bit (dual-octal) noninverting bus transceiver contains two separate supply rails. B port has VCCB, which is set to operate at 3.3 V and 5 V. A port has VCCA, which is set to operate at 2.5 V and 3.3 V. This allows for translation from a 2.5-V to a 3.3-V environment, and vice versa, or from a 3.3-V to a 5-V environment, and vice versa.

The SN74ALVC164245 is designed for asynchronous communication between data buses. The control circuitry (1DIR, 2DIR, 1OE, and 2OE) is powered by VCCA.

To ensure the high-impedance state during power up or power down, the output-enable (OE) input should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.

This 16-bit (dual-octal) noninverting bus transceiver contains two separate supply rails. B port has VCCB, which is set to operate at 3.3 V and 5 V. A port has VCCA, which is set to operate at 2.5 V and 3.3 V. This allows for translation from a 2.5-V to a 3.3-V environment, and vice versa, or from a 3.3-V to a 5-V environment, and vice versa.

The SN74ALVC164245 is designed for asynchronous communication between data buses. The control circuitry (1DIR, 2DIR, 1OE, and 2OE) is powered by VCCA.

To ensure the high-impedance state during power up or power down, the output-enable (OE) input should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.
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Top-Dokumentation Typ Titel Format-Optionen Neueste englische Version herunterladen Datum
* Datenblatt SN74ALVC164245 16-Bit 2.5-V to 3.3-V or 3.3-V to 5-V Level-Shifting Transceiver With 3-State Outputs datasheet (Rev. Q) PDF | HTML 27.09.2016
Anwendungshinweis Schematic Checklist - A Guide to Designing With Fixed or Direction Control Translators PDF | HTML 02.10.2024
Anwendungshinweis Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators PDF | HTML 12.07.2024
Anwendungshinweis Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) PDF | HTML 03.07.2024
Auswahlhilfe Voltage Translation Buying Guide (Rev. A) 15.04.2021

Design und Entwicklung

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Simulationsmodell

SN74ALVC164245 IBIS Model (Rev. C)

SCEM026A (11 KB) - IBIS-Modell
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SSOP (DL) 48 Ultra Librarian
TSSOP (DGG) 48 Ultra Librarian
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