SN74ALVCH162374

Name: SN74ALVCH162374
Brand: TI
SKU: SN74ALVCH162374
Price: 0.806 USD

AKTIV

Taktflankengesteuertes D-Flipflop, 16 Bit, mit Tri-State-Ausgängen

Jetzt bestellen

Datenblatt

document-pdfAcrobat SN74ALVCH162374 datasheet (Rev. F) (Englisch)

SN74ALVCH162374

AKTIV

Datenblatt

Jetzt bestellen

Produktdetails

Number of channels

16

Technology family

ALVC

Supply voltage (min) (V)

1.65

Supply voltage (max) (V)

3.6

Input type

Standard CMOS

Output type

3-State

Clock frequency (max) (MHz)

150

IOL (max) (mA)

12

IOH (max) (mA)

-12

Supply current (max) (µA)

40

Features

Balanced outputs, Bus-hold, Damping resistors, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns)

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Number of channels

16

Technology family

ALVC

Supply voltage (min) (V)

1.65

Supply voltage (max) (V)

3.6

Input type

Standard CMOS

Output type

3-State

Clock frequency (max) (MHz)

150

IOL (max) (mA)

12

IOH (max) (mA)

-12

Supply current (max) (µA)

40

Features

Balanced outputs, Bus-hold, Damping resistors, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns)

Operating temperature range (°C)

-40 to 85

Rating

Catalog

SSOP (DL)

48

164.358 mm² 15.88 x 10.35

TSSOP (DGG)

48

101.25 mm² 12.5 x 8.1

Member of the Texas Instruments Widebus™ Family
Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
Output Ports Have Equivalent 26- Series Resistors, So No External Resistors Are Required
Latch-Up Performance Exceeds 250 mA Per JESD 17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)

Widebus is a trademark of Texas Instruments.

Member of the Texas Instruments Widebus™ Family
Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
Output Ports Have Equivalent 26- Series Resistors, So No External Resistors Are Required
Latch-Up Performance Exceeds 250 mA Per JESD 17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)

Widebus is a trademark of Texas Instruments.

This 16-bit edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V V_CC operation.

The SN74ALVCH162374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. It can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up at the data (D) inputs.

The output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. OE\ does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

The outputs, which are designed to sink up to 12 mA, include equivalent 26- resistors to reduce overshoot and undershoot.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

This 16-bit edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V V_CC operation.

The SN74ALVCH162374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. It can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up at the data (D) inputs.

The output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. OE\ does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

The outputs, which are designed to sink up to 12 mA, include equivalent 26- resistors to reduce overshoot and undershoot.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

open-in-new

Andere D-Typ-Flipflops suchen

Herunterladen Video mit Transkript ansehen Video

Alle anzeigen 20

	Typ	Titel		Datum
*	Data sheet	SN74ALVCH162374 datasheet (Rev. F)		01 Sep 2004
	Application note	Power-Up Behavior of Clocked Devices (Rev. B)	PDF \| HTML	15 Dez 2022
	Application note	An Overview of Bus-Hold Circuit and the Applications (Rev. B)		17 Sep 2018
	Selection guide	Logic Guide (Rev. AB)		12 Jun 2017
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)		02 Dez 2015
	User guide	LOGIC Pocket Data Book (Rev. B)		16 Jan 2007
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection		08 Jul 2004
	Application note	TI IBIS File Creation, Validation, and Distribution Processes		29 Aug 2002
	User guide	ALVC Advanced Low-Voltage CMOS Including SSTL, HSTL, And ALB (Rev. B)		01 Aug 2002
	More literature	Standard Linear & Logic for PCs, Servers & Motherboards		13 Jun 2002
	Application note	16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)		22 Mai 2002
	Application note	Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A)		08 Sep 1999
	Application note	TI SN74ALVC16835 Component Specification Analysis for PC100		03 Aug 1998
	Application note	Logic Solutions for PC-100 SDRAM Registered DIMMs (Rev. A)		13 Mai 1998
	Application note	Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices		01 Dez 1997
	Application note	Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)		01 Aug 1997
	Application note	CMOS Power Consumption and CPD Calculation (Rev. B)		01 Jun 1997
	Application note	Input and Output Characteristics of Digital Integrated Circuits		01 Okt 1996
	Application note	Live Insertion		01 Okt 1996
	Application note	Understanding Advanced Bus-Interface Products Design Guide		01 Mai 1996

Design und Entwicklung

Weitere Bedingungen oder erforderliche Ressourcen enthält gegebenenfalls die Detailseite, die Sie durch Klicken auf einen der unten stehenden Titel erreichen.