Produktdetails

Technology family AS Bits (#) 8 Rating Catalog Operating temperature range (°C) 0 to 70
Technology family AS Bits (#) 8 Rating Catalog Operating temperature range (°C) 0 to 70
SOIC (DW) 24 159.65 mm² 15.5 x 10.3
  • Latchable P-Input Ports With Power-Up Clear
  • Choice of Logical or Arithmetic
    (Two's Complement) Comparison
  • Data and PLE Inputs Utilize pnp Input Transistors to Reduce dc Loading Effects
  • Approximately 35% Improvement in
    ac Performance Over Schottky TTL While Performing More Functions
  • Cascadable to n Bits While Maintaining High Performance
  • 10% Less Power Than STTL for an 8-Bit Comparison
  • Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (NT) and Ceramic (JT) 300-mil DIPs

 

  • Latchable P-Input Ports With Power-Up Clear
  • Choice of Logical or Arithmetic
    (Two's Complement) Comparison
  • Data and PLE Inputs Utilize pnp Input Transistors to Reduce dc Loading Effects
  • Approximately 35% Improvement in
    ac Performance Over Schottky TTL While Performing More Functions
  • Cascadable to n Bits While Maintaining High Performance
  • 10% Less Power Than STTL for an 8-Bit Comparison
  • Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (NT) and Ceramic (JT) 300-mil DIPs

 

These advanced Schottky devices are capable of performing high-speed arithmetic or logic comparisons on two 8-bit binary or two's complement words. Two fully decoded decisions about words P and Q are externally available at two outputs. These devices are fully expandable to any number of bits without external gates. To compare words of longer lengths, the P > QOUT and P < QOUT outputs of a stage handling less significant bits can be connected to the P > QIN and P < QIN inputs of the next stage handling more significant bits. The cascading paths are implemented with only a two-gate-level delay to reduce overall comparison times for long words. Two alternative methods of cascading are shown in application information.

The latch is transparent when P latch-enable (PLE) input is high; the P-input port is latched

when PLE is low. This provides the designer with temporary storage for the P-data word. The enable circuitry is implemented with minimal delay times to enhance performance when cascaded for longer words. The PLE, P, and Q data inputs utilize pnp input transistors to reduce the low-level current input requirement to typically -0.25 mA, which minimizes dc loading effects.

The SN54AS885 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74AS885 is characterized for operation from 0°C to 70°C.

 

 

In these cases, P > QOUT follows P > QIN and P < QOUT follows P < QIN.

AG = arithmetically greater than

These advanced Schottky devices are capable of performing high-speed arithmetic or logic comparisons on two 8-bit binary or two's complement words. Two fully decoded decisions about words P and Q are externally available at two outputs. These devices are fully expandable to any number of bits without external gates. To compare words of longer lengths, the P > QOUT and P < QOUT outputs of a stage handling less significant bits can be connected to the P > QIN and P < QIN inputs of the next stage handling more significant bits. The cascading paths are implemented with only a two-gate-level delay to reduce overall comparison times for long words. Two alternative methods of cascading are shown in application information.

The latch is transparent when P latch-enable (PLE) input is high; the P-input port is latched

when PLE is low. This provides the designer with temporary storage for the P-data word. The enable circuitry is implemented with minimal delay times to enhance performance when cascaded for longer words. The PLE, P, and Q data inputs utilize pnp input transistors to reduce the low-level current input requirement to typically -0.25 mA, which minimizes dc loading effects.

The SN54AS885 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74AS885 is characterized for operation from 0°C to 70°C.

 

 

In these cases, P > QOUT follows P > QIN and P < QOUT follows P < QIN.

AG = arithmetically greater than

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Technische Dokumentation

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Alle anzeigen 11
Typ Titel Datum
* Data sheet 8-Bit Magnitude Comparators datasheet (Rev. A) 01 Jan 1995
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dez 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note Advanced Schottky Load Management 01 Feb 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Okt 1996
Application note Live Insertion 01 Okt 1996
Application note Advanced Schottky (ALS and AS) Logic Families 01 Aug 1995

Design und Entwicklung

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Das 14-24-LOGIC-EVM-Evaluierungsmodul (EVM) ist für die Unterstützung aller Logikgeräte konzipiert, die sich in einem 14-Pin- bis 24-Pin-D-, DW-, DB-, NS-, PW-, DYY- oder DGV-Gehäuse befinden.

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