SN74CBTLV16211

AKTIV

Produktdetails

Protocols Analog Configuration 1:1 SPST Number of channels 24 Bandwidth (MHz) 200 Ron (typ) (mΩ) 5000 Input/output voltage (min) (V) 0 Input/output voltage (max) (V) 3.6 Operating temperature range (°C) -40 to 85 Input/output continuous current (max) (mA) 128 COFF (typ) (pF) 6.5 OFF-state leakage current (max) (µA) 1 Ron (max) (mΩ) 40000 VIH (min) (V) 2 VIL (max) (V) 0.8 Rating Catalog
Protocols Analog Configuration 1:1 SPST Number of channels 24 Bandwidth (MHz) 200 Ron (typ) (mΩ) 5000 Input/output voltage (min) (V) 0 Input/output voltage (max) (V) 3.6 Operating temperature range (°C) -40 to 85 Input/output continuous current (max) (mA) 128 COFF (typ) (pF) 6.5 OFF-state leakage current (max) (µA) 1 Ron (max) (mΩ) 40000 VIH (min) (V) 2 VIL (max) (V) 0.8 Rating Catalog
SSOP (DL) 56 190.647 mm² (18.42 mm × 10.35 mm) TVSOP (DGV) 56 72.32 mm² (11.3 mm × 6.4 mm) TSSOP (DGG) 56 113.4 mm² (14 mm × 8.1 mm)
  • Member of the Texas Instruments Widebus™ Family
  • 5- Switch Connection Between Two Ports
  • Rail-to-Rail Switching on Data I/O Ports
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)

Widebus is a trademark of Texas Instruments.

  • Member of the Texas Instruments Widebus™ Family
  • 5- Switch Connection Between Two Ports
  • Rail-to-Rail Switching on Data I/O Ports
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)

Widebus is a trademark of Texas Instruments.

The SN74CBTLV16211 provides 24 bits of high-speed bus switching. The low on-state resistance of the switch allows connections to be made with minimal propagation delay.

The device is organized as dual 12-bit bus switches with separate output-enable (OE\) inputs. It can be used as two 12-bit bus switches or as one 24-bit bus switch. When OE\ is low, the associated 12-bit bus switch is on, and port A is connected to port B. When OE\ is high, the switch is open, and the high-impedance state exists between the two ports.

This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74CBTLV16211 provides 24 bits of high-speed bus switching. The low on-state resistance of the switch allows connections to be made with minimal propagation delay.

The device is organized as dual 12-bit bus switches with separate output-enable (OE\) inputs. It can be used as two 12-bit bus switches or as one 24-bit bus switch. When OE\ is low, the associated 12-bit bus switch is on, and port A is connected to port B. When OE\ is high, the switch is open, and the high-impedance state exists between the two ports.

This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

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Technische Dokumentation

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Top-Dokumentation Typ Titel Format-Optionen Neueste englische Version herunterladen Datum
* Datenblatt SN74CBTLV16211 datasheet (Rev. I) 10.10.2003
Anwendungshinweis Selecting the Correct Texas Instruments Signal Switch (Rev. E) PDF | HTML 02.06.2022
Anwendungshinweis Multiplexers and Signal Switches Glossary (Rev. B) PDF | HTML 01.12.2021
Application brief Eliminate Power Sequencing with Powered-off Protection Signal Switches (Rev. C) PDF | HTML 06.01.2021

Design und Entwicklung

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Simulationsmodell

HSPICE Model of SN74CBTLV16211

SCDJ016.ZIP (42 KB) - HSpice-Modell
Unterstützte Produkte und Hardware
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SN74CBTLV16211 IBIS Model

SCDM018.ZIP (25 KB) - IBIS-Modell
Unterstützte Produkte und Hardware
Gehäuse Pins CAD-Symbole, Footprints und 3D-Modelle
SSOP (DL) 56 Ultra Librarian
TVSOP (DGV) 56 Ultra Librarian
TSSOP (DGG) 56 Ultra Librarian

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