SN74LVC1G86-Q1

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XOR-Gate mit 2 Eingängen, 1,65 V bis 5,5 V (Exklusiv OR) für die Automobilindustrie

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Datenblatt

document-pdfAcrobat SN74LVC1G86 -Q1 Single 2-Input Exclusive-OR Gate datasheet (Rev. A) (Englisch) PDF | HTML

SN74LVC1G86-Q1

AKTIV

Datenblatt

Jetzt bestellen

Produktdetails

Technology family

LVC

Number of channels

1

Inputs per channel

2

IOL (max) (mA)

32

Input type

Standard CMOS

IOH (max) (mA)

-32

Output type

Push-Pull

Features

Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns)

Data rate (max) (Mbps)

100

Rating

Automotive

Operating temperature range (°C)

-40 to 125

Technology family

LVC

Number of channels

1

Inputs per channel

2

IOL (max) (mA)

32

Input type

Standard CMOS

IOH (max) (mA)

-32

Output type

Push-Pull

Features

Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns)

Data rate (max) (Mbps)

100

Rating

Automotive

Operating temperature range (°C)

-40 to 125

SOT-SC70 (DCK)

5

4.2 mm² (2 mm × 2.1 mm)

Qualified for Automotive Applications
Supports 5V VCC operation
Inputs are over voltage tolerant up to 5.5V
Supports down translation to VCC
Low power consumption, 15µA maximum ICC
Maximum tpd of 6ns at 3.3V and 50pF load
±24mA output drive at 3.3V
Ioff supports partial-power-down mode, and back-drive protection
Latch-up performance exceeds 100mA per JESD 78, Class II

Qualified for Automotive Applications
Supports 5V VCC operation
Inputs are over voltage tolerant up to 5.5V
Supports down translation to VCC
Low power consumption, 15µA maximum ICC
Maximum tpd of 6ns at 3.3V and 50pF load
±24mA output drive at 3.3V
Ioff supports partial-power-down mode, and back-drive protection
Latch-up performance exceeds 100mA per JESD 78, Class II

The SN74LVC1G86-Q1 is an automotive qualified device that performs the Boolean function Y = AB + A B in positive logic. This single 2-input exclusive-OR gate is designed for 1.65V to 5.5V VCC operation.

If the input is low, the other input is reproduced in true form at the output. If the input is high, the signal on the other input is reproduced inverted at the output. This device has low power consumption with maximum tpd of 6ns at 3.3V and 50pF capacitive load. The maximum output drive is ±32mA at 4.5V and ±24mA at 3.3V.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current back flow through the device when it is powered down.

The SN74LVC1G86-Q1 is an automotive qualified device that performs the Boolean function Y = AB + A B in positive logic. This single 2-input exclusive-OR gate is designed for 1.65V to 5.5V VCC operation.

If the input is low, the other input is reproduced in true form at the output. If the input is high, the signal on the other input is reproduced inverted at the output. This device has low power consumption with maximum tpd of 6ns at 3.3V and 50pF capacitive load. The maximum output drive is ±32mA at 4.5V and ±24mA at 3.3V.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current back flow through the device when it is powered down.

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Top-Dokumentation	Typ	Titel	Format-Optionen	Neueste englische Version herunterladen	Datum
*	Datenblatt	SN74LVC1G86 -Q1 Single 2-Input Exclusive-OR Gate datasheet (Rev. A)	PDF \| HTML		14.08.2026

Design und Entwicklung

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