TPS3837K33-EP

The TPS3836, TPS3837, TPS3838 families of supervisory circuits provide circuit initialization and timing supervision, primarily for digital signal processing (DSP) and processor-based systems.

During power on, RESET is asserted when the supply voltage V_DD becomes higher than 1.1 V. Thereafter, the supervisory circuit monitors V_DD and keeps RESET output active as long as V_DD remains below the threshold voltage (V_IT). An internal timer delays the return of the output to the inactive state (high) to ensure proper system reset. The delay time starts after V_DD has risen above V_IT.

When CT is connected to GND, a fixed delay time of typical 10 ms is asserted. When connected to V_DD, the delay time is typically 200 ms.

When the supply voltage drops below V_IT, the output becomes active (low) again.

All the devices of this family have a fixed-sense V_IT set by an internal voltage divider.

The TPS3836 has an active-low push-pull RESET output. The TPS3837 has active-high push-pull RESET, and the TPS3838 integrates an active-low open-drain RESET output.

The product spectrum is designed for supply voltages of 1.8 V, 2.5 V, 3 V, and 3.3 V. The circuits are available in a 5-pin SOT-23 package. The TPS3836, TPS3837, and TPS3838 families are characterized for operation over a temperature range of –55°C to 125°C.