The TPS702xx is a low dropout voltage regulator with integrated SVS (RESET, POR, or power on reset) and power good (PG) functions. These devices are capable of supplying 500mA and 250mA by regulator 1 and regulator 2 respectively. Quiescent current is typically 190µA at full load. Differentiated features, such as accuracy, fast transient response, SVS supervisory circuit (power on reset), manual reset input, and independent enable functions provide a complete system solution.
The TPS702xx family of voltage regulators offers very low dropout voltage and dual outputs. These devices have extremely low noise output performance without using any added filter bypass capacitors and are designed to have a fast transient response and be stable with 10µF low ESR capacitors.
These devices have fixed 3.3V/2.5V, 3.3V/1.8V, 3.3V/1.5V, 3.3V/1.2V, and adjustable voltage options. Regulator 1 can support up to 500mA, and regulator 2 can support up to 250mA. Separate voltage inputs allow the designer to configure the source power.
Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 170mV on regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (maximum of 230µA over the full range of output current and full range of temperature). This LDO family also features a sleep mode; applying a high signal to EN1 or EN2 (enable) shuts down regulator 1 or regulator 2, respectively. When a high signal is applied to both EN1 and EN2, both regulators enter sleep mode, thereby reducing the input current to 2µA at TJ = +25°C.
For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator is turned off (disabled).
The PG1 pin reports the voltage condition at VOUT1. The PG1 pin can be used to implement a SVS (RESET, POR, or power on reset) for the circuitry supplied by regulator 1. The PG2 pin reports the voltage conditions at VOUT2. The PG2 pin can be used to implement a SVS (power on reset) for the circuitry supplied by regulator 2.
The TPS702xx features a RESET (SVS, POR, or power on reset). RESET output initiates a reset in the event of an undervoltage condition. RESET also indicates the status of the manual reset pin (MR). When MR is in the logic high state, RESET goes to a high impedance state after a 120ms delay. To monitor VOUT1, the PG1 output pin can be connected to MR. To monitor VOUT2, the PG2 output pin can be connected to MR.
The device has an undervoltage lockout UVLO circuit that prevents the internal regulators from turning on until VIN1 reaches 2.5V.
| Typ | Titel | Datum | ||
|---|---|---|---|---|
| * | Data sheet | Dual-Output, Low-Dropout Voltage Regulators datasheet (Rev. E) | 06 Dez 2009 | |
| Application note | LDO Noise Demystified (Rev. B) | PDF | HTML | 18 Aug 2020 | |
| Application note | LDO PSRR Measurement Simplified (Rev. A) | PDF | HTML | 09 Aug 2017 | |
| Application note | Power Supply Sequencing Solutions for Dual Supply Voltage DSPs (Rev. A) | 05 Jul 2000 |
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| Gehäuse | Pins | Herunterladen |
|---|---|---|
| HTSSOP (PWP) | 20 | Optionen anzeigen |
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