ADS4229

ACTIVO

Convertidor analógico a digital (ADC) de dos canales, 12 bits y 250 MSPS

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Hoja de datos

document-pdfAcrobat ADS4229 Dual-Channel, 12-Bit, 250-MSPS Ultralow-Power ADC datasheet (Rev. C) (Inglés) PDF | HTML

Guías de usuario

document-pdfAcrobat
Interfacing Altera FPGAs to ADS4249 and DAC3482 (TIDA-00069 Reference Guide) (Inglés)

ADS4229

ACTIVO

Hoja de datos

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Detalles del producto

Sample rate (max) (Msps)

250

Resolution (Bits)

12

Number of input channels

2

Interface type

DDR LVDS, Parallel CMOS

Analog input BW (MHz)

600

Features

Low Power

Rating

Catalog

Peak-to-peak input voltage range (V)

2

Power consumption (typ) (mW)

470

Architecture

Pipeline

SNR (dB)

70.5

ENOB (Bits)

11.15

SFDR (dB)

80.8

Operating temperature range (°C)

-40 to 85

Input buffer

No

Sample rate (max) (Msps)

250

Resolution (Bits)

12

Number of input channels

2

Interface type

DDR LVDS, Parallel CMOS

Analog input BW (MHz)

600

Features

Low Power

Rating

Catalog

Peak-to-peak input voltage range (V)

2

Power consumption (typ) (mW)

470

Architecture

Pipeline

SNR (dB)

70.5

ENOB (Bits)

11.15

SFDR (dB)

80.8

Operating temperature range (°C)

-40 to 85

Input buffer

No

VQFN (RGC)

64

81 mm² (9 mm × 9 mm)

Maximum Sample Rate: 250 MSPS
Ultralow Power with Single 1.8-V Supply:
- 545-mW Total Power at 250 MSPS
High Dynamic Performance:
- 80.8-dBc SFDR at 170 MHz
- 69.4-dBFS SNR at 170 MHz
Crosstalk: > 90 dB at 185 MHz
Programmable Gain Up to 6 dB for
SNR and SFDR Trade-off
DC Offset Correction
Output Interface Options:
- 1.8-V Parallel CMOS Interface
- DDR LVDS With Programmable Swing:
  - Standard Swing: 350 mV
  - Low Swing: 200 mV
Supports Low Input Clock Amplitude
Down to 200 mV_PP
Package: 9-mm × 9-mm, 64-Pin Quad Flat
No-Lead (QFN) Package

Maximum Sample Rate: 250 MSPS
Ultralow Power with Single 1.8-V Supply:
- 545-mW Total Power at 250 MSPS
High Dynamic Performance:
- 80.8-dBc SFDR at 170 MHz
- 69.4-dBFS SNR at 170 MHz
Crosstalk: > 90 dB at 185 MHz
Programmable Gain Up to 6 dB for
SNR and SFDR Trade-off
DC Offset Correction
Output Interface Options:
- 1.8-V Parallel CMOS Interface
- DDR LVDS With Programmable Swing:
  - Standard Swing: 350 mV
  - Low Swing: 200 mV
Supports Low Input Clock Amplitude
Down to 200 mV_PP
Package: 9-mm × 9-mm, 64-Pin Quad Flat
No-Lead (QFN) Package

The ADS4229 is a member of the ADS42xx ultralow-power family of dual-channel, 12-bit and 14-bit analog-to-digital converters (ADCs). Innovative design techniques are used to achieve high dynamic performance, while consuming extremely low power with a 1.8-V supply. This topology makes the ADS4229 well-suited for multi-carrier, wide-bandwidth communications applications.

The ADS4229 has gain options that can be used to improve spurious-free dynamic range (SFDR) performance at lower full-scale input ranges. This device also includes a dc offset correction loop that can be used to cancel the ADC offset. Both double data rate (DDR) low-voltage differential signaling (LVDS) and parallel complementary metal oxide semiconductor (CMOS) digital output interfaces are available in a compact QFN-64 PowerPAD™ package.

The device includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. The ADS4229 is specified over the industrial temperature range (–40°C to +85°C).

The ADS4229 is a member of the ADS42xx ultralow-power family of dual-channel, 12-bit and 14-bit analog-to-digital converters (ADCs). Innovative design techniques are used to achieve high dynamic performance, while consuming extremely low power with a 1.8-V supply. This topology makes the ADS4229 well-suited for multi-carrier, wide-bandwidth communications applications.

The ADS4229 has gain options that can be used to improve spurious-free dynamic range (SFDR) performance at lower full-scale input ranges. This device also includes a dc offset correction loop that can be used to cancel the ADC offset. Both double data rate (DDR) low-voltage differential signaling (LVDS) and parallel complementary metal oxide semiconductor (CMOS) digital output interfaces are available in a compact QFN-64 PowerPAD™ package.

The device includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. The ADS4229 is specified over the industrial temperature range (–40°C to +85°C).

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Documentación técnica

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Documentación principal	Tipo	Título	Opciones de formato	Fecha
*	Hoja de datos	ADS4229 Dual-Channel, 12-Bit, 250-MSPS Ultralow-Power ADC datasheet (Rev. C)	PDF \| HTML	28/05/2015
*	Guía del usuario	Interfacing Altera FPGAs to ADS4249 and DAC3482 (TIDA-00069 Reference Guide)		10/07/2012
	Nota sobre la aplicación	Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)		22/05/2015
	Nota sobre la aplicación	Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)		19/07/2013
	Nota sobre la aplicación	High-Speed, Analog-to-Digital Converter Basics		11/01/2012
	Nota sobre la aplicación	Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)		10/09/2010
	Nota sobre la aplicación	Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio		28/04/2009
	Nota sobre la aplicación	CDCE62005 as Clock Solution for High-Speed ADCs		4/09/2008
	Nota sobre la aplicación	CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters		8/06/2008
	Nota sobre la aplicación	Phase Noise Performance and Jitter Cleaning Ability of CDCE72010		2/06/2008
	Nota sobre la aplicación	QFN Layout Guidelines		28/07/2006

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

GUI para el módulo de evaluación (EVM)

ADS58C28SPIGUI-SW — ADS42xxx SPI GUI

ADS58C28SPIGUI-SW is the installation package for ADS58C28_ADS42xx_GUI which is used to access or write internal registers of ADS58C28 through an on-board USB port.