ADS5270

ACTIVO

Convertidor analógico a digital (ADC) de ocho canales, 12 bits y 40 MSPS

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Hoja de datos

document-pdfAcrobat 8-Channel, 12-Bit, 40MSPS Analog-to-Digital Converter with Serial LVDS Interface datasheet (Rev. F) (Inglés)

ADS5270

ACTIVO

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Detalles del producto

Sample rate (max) (Msps)

40

Resolution (Bits)

12

Number of input channels

8

Interface type

Parallel LVDS

Analog input BW (MHz)

300

Features

Low Power

Rating

Catalog

Peak-to-peak input voltage range (V)

2

Power consumption (typ) (mW)

907

Architecture

Pipeline

SNR (dB)

70.5

ENOB (Bits)

11.3

SFDR (dB)

89

Operating temperature range (°C)

-40 to 85

Input buffer

No

Sample rate (max) (Msps)

40

Resolution (Bits)

12

Number of input channels

8

Interface type

Parallel LVDS

Analog input BW (MHz)

300

Features

Low Power

Rating

Catalog

Peak-to-peak input voltage range (V)

2

Power consumption (typ) (mW)

907

Architecture

Pipeline

SNR (dB)

70.5

ENOB (Bits)

11.3

SFDR (dB)

89

Operating temperature range (°C)

-40 to 85

Input buffer

No

HTQFP (PFP)

80

196 mm² (14 mm × 14 mm)

Maximum Sample Rate: 40MSPS
12-Bit Resolution
No Missing Codes
Total Power Dissipation:
Internal Reference: 888mW
External Reference: 822mW
CMOS Technology
Simultaneous Sample-and-Hold
70.5dB SNR at 10MHz IF
3.3V Digital/Analog Supply
Serialized LVDS Outputs
Integrated Frame and Bit Patterns
Option to Double LVDS Clock Output Currents
Four Current Modes for LVDS
Pin- and Format-Compatible Family
TQFP-80 PowerPAD Package

Maximum Sample Rate: 40MSPS
12-Bit Resolution
No Missing Codes
Total Power Dissipation:
Internal Reference: 888mW
External Reference: 822mW
CMOS Technology
Simultaneous Sample-and-Hold
70.5dB SNR at 10MHz IF
3.3V Digital/Analog Supply
Serialized LVDS Outputs
Integrated Frame and Bit Patterns
Option to Double LVDS Clock Output Currents
Four Current Modes for LVDS
Pin- and Format-Compatible Family
TQFP-80 PowerPAD Package

The ADS5270 is a high-performance, 40MSPS, 8-channel analog-to-digital converter (ADC). Internal references are provided, simplifying system design requirements. Low power consumption allows for the highest of system integration densities. Serial LVDS (low-voltage differential signaling) outputs reduce the number of interface lines and package size.

An integrated phase lock loop (PLL) multiplies the incoming ADC sampling clock by a factor of 12. This high-frequency LVDS clock is used in the data serialization and transmission process. The word output of each internal ADC is serialized and transmitted either MSB or LSB first. In addition to the eight data outputs, a bit clock and a word clock are also transmitted. The bit clock is at 6x the speed of the sampling clock, whereas the word clock is at the same speed of the sampling clock.

The ADS5270 provides internal references, or can optionally be driven with external references. Best performance can be achieved through the internal reference mode.

The device is available in a TQFP-80 PowerPAD package and is specified over a -40°C to +85°C operating range.

The ADS5270 is a high-performance, 40MSPS, 8-channel analog-to-digital converter (ADC). Internal references are provided, simplifying system design requirements. Low power consumption allows for the highest of system integration densities. Serial LVDS (low-voltage differential signaling) outputs reduce the number of interface lines and package size.

An integrated phase lock loop (PLL) multiplies the incoming ADC sampling clock by a factor of 12. This high-frequency LVDS clock is used in the data serialization and transmission process. The word output of each internal ADC is serialized and transmitted either MSB or LSB first. In addition to the eight data outputs, a bit clock and a word clock are also transmitted. The bit clock is at 6x the speed of the sampling clock, whereas the word clock is at the same speed of the sampling clock.

The ADS5270 provides internal references, or can optionally be driven with external references. Best performance can be achieved through the internal reference mode.

The device is available in a TQFP-80 PowerPAD package and is specified over a -40°C to +85°C operating range.

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Documentación técnica

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Ver todo 13

Documentación principal	Tipo	Título
*	Hoja de datos	8-Channel, 12-Bit, 40MSPS Analog-to-Digital Converter with Serial LVDS Interface datasheet (Rev. F)	6/01/2009
	Nota sobre la aplicación	Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)	22/05/2015
	Nota sobre la aplicación	Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)	19/07/2013
	Nota sobre la aplicación	Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)	10/09/2010
	Nota sobre la aplicación	Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio	28/04/2009
	Nota sobre la aplicación	CDCE62005 as Clock Solution for High-Speed ADCs	4/09/2008
	Nota sobre la aplicación	CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters	8/06/2008
	Nota sobre la aplicación	Phase Noise Performance and Jitter Cleaning Ability of CDCE72010	2/06/2008
	Nota sobre la aplicación	Interfacing the VCA8613 with High-Speed ADCs	5/04/2005
	Nota sobre la aplicación	Interfacing the VCA8617 with High-Speed ADCs	5/04/2005
	Nota sobre la aplicación	Interfacing High-Speed LVDS Outputs of the ADS527x/ADS524x	23/02/2005
	Nota sobre la aplicación	Using the ADSDeSer-50EVM to Deserialize ADS527x 10-Bit Outputs	8/07/2004
	Nota sobre la aplicación	LVDS Outputs on the ADS527x	10/06/2004

Diseño y desarrollo

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