ADS5413

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Convertidor analógico a digital (ADC) de 12 bits, 65 MSPS y ancho de banda de entrada de 1,0 GHz

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Hoja de datos

document-pdfAcrobat ADS5413: 12-bit, 65 MSPS CommsADC Analog-to-Digital Converter datasheet (Inglés)

ADS5413

ACTIVO

Hoja de datos

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Detalles del producto

Sample rate (max) (Msps)

65

Resolution (Bits)

12

Number of input channels

1

Interface type

Parallel CMOS

Analog input BW (MHz)

1000

Features

Low Power

Rating

Catalog

Peak-to-peak input voltage range (V)

2.25

Power consumption (typ) (mW)

400

Architecture

Pipeline

SNR (dB)

68.5

ENOB (Bits)

11.3

SFDR (dB)

81

Operating temperature range (°C)

-40 to 85

Input buffer

No

Sample rate (max) (Msps)

65

Resolution (Bits)

12

Number of input channels

1

Interface type

Parallel CMOS

Analog input BW (MHz)

1000

Features

Low Power

Rating

Catalog

Peak-to-peak input voltage range (V)

2.25

Power consumption (typ) (mW)

400

Architecture

Pipeline

SNR (dB)

68.5

ENOB (Bits)

11.3

SFDR (dB)

81

Operating temperature range (°C)

-40 to 85

Input buffer

No

HTQFP (PHP)

48

81 mm² (9 mm × 9 mm)

12-Bit Resolution
65-MSPS Maximum Sample Rate
2-Vpp Differential Input Range
3.3-V Single Supply Operation
1.8-V to 3.3-V Output Supply
400-mW Total Power Dissipation
Two’s Complement Output Format
On-Chip S/H and Duty Cycle Adjust Circuit
Internal or External Reference
48-Pin TQFP Package With PowerPad
(7 mm x 7 mm body size)
64.5-dBFS SNR and 72-dBc SFDR at 65 MSPS and 190-MHz Input
Power-Down Mode
Single-Ended or Differential Clock
1-GHz -3-dB Input Bandwidth
APPLICATIONS
- High IF Sampling Receivers
- Medical Imaging
- Portable Instrumentation

CommsADC is a trademark of Texas Instruments.

12-Bit Resolution
65-MSPS Maximum Sample Rate
2-Vpp Differential Input Range
3.3-V Single Supply Operation
1.8-V to 3.3-V Output Supply
400-mW Total Power Dissipation
Two’s Complement Output Format
On-Chip S/H and Duty Cycle Adjust Circuit
Internal or External Reference
48-Pin TQFP Package With PowerPad
(7 mm x 7 mm body size)
64.5-dBFS SNR and 72-dBc SFDR at 65 MSPS and 190-MHz Input
Power-Down Mode
Single-Ended or Differential Clock
1-GHz -3-dB Input Bandwidth
APPLICATIONS
- High IF Sampling Receivers
- Medical Imaging
- Portable Instrumentation

CommsADC is a trademark of Texas Instruments.

The ADS5413 is a low power, 12-bit, 65-MSPS, CMOS pipeline analog-to-digital converter (ADC) that operates from a single 3.3-V supply, while offering the choice of digital output levels from 1.8 V to 3.3 V. The low noise, high linearity, and low clock jitter makes the ADC well suited for high-input frequency sampling applications. On-chip duty cycle adjust circuit allows the use of a non-50% duty cycle. This can be bypassed for applications requiring low jitter or asynchronous sampling. The device can also be clocked with single ended or differential clock, without change in performance. The internal reference can be bypassed to use an external reference to suit the accuracy and low drift requirements of the application.

The device is specified over full temperature range (–40°C to +85°C).

The ADS5413 is a low power, 12-bit, 65-MSPS, CMOS pipeline analog-to-digital converter (ADC) that operates from a single 3.3-V supply, while offering the choice of digital output levels from 1.8 V to 3.3 V. The low noise, high linearity, and low clock jitter makes the ADC well suited for high-input frequency sampling applications. On-chip duty cycle adjust circuit allows the use of a non-50% duty cycle. This can be bypassed for applications requiring low jitter or asynchronous sampling. The device can also be clocked with single ended or differential clock, without change in performance. The internal reference can be bypassed to use an external reference to suit the accuracy and low drift requirements of the application.

The device is specified over full temperature range (–40°C to +85°C).

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Documentación técnica

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Documentación principal	Tipo	Título	Fecha
*	Hoja de datos	ADS5413: 12-bit, 65 MSPS CommsADC Analog-to-Digital Converter datasheet	16/12/2003
	Nota sobre la aplicación	Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)	22/05/2015
	Nota sobre la aplicación	Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)	19/07/2013
	Nota sobre la aplicación	High-Speed, Analog-to-Digital Converter Basics	11/01/2012
	Nota sobre la aplicación	Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)	10/09/2010
	Nota sobre la aplicación	Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio	28/04/2009
	Nota sobre la aplicación	CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters	8/06/2008
	Nota sobre la aplicación	Phase Noise Performance and Jitter Cleaning Ability of CDCE72010	2/06/2008
	Nota sobre la aplicación	Standard Procedure Direct Measurement Sub-picosecond RMS Jitter High-Speed ADC	30/06/2004
	Nota sobre la aplicación	How to Calculate the Period Jitter from the SSCR for High-Speed ADCs	17/12/2003

Diseño y desarrollo

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