ADS62P15

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Convertidor analógico a digital (ADC) de dos canales, 11 bits y 125 MSPS

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Hoja de datos

document-pdfAcrobat Dual Channel 11-Bits 125-MSPS ADC w/parallel CMOS / DDR LVDS Outputs datasheet (Rev. C) (Inglés)

ADS62P15

ACTIVO

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Detalles del producto

Sample rate (max) (Msps)

125

Resolution (Bits)

11

Number of input channels

2

Interface type

DDR LVDS, Parallel CMOS

Analog input BW (MHz)

450

Features

Low Power

Rating

Catalog

Peak-to-peak input voltage range (V)

2

Power consumption (typ) (mW)

740

Architecture

Pipeline

SNR (dB)

67.2

ENOB (Bits)

10.8

SFDR (dB)

89

Operating temperature range (°C)

-40 to 85

Input buffer

No

Sample rate (max) (Msps)

125

Resolution (Bits)

11

Number of input channels

2

Interface type

DDR LVDS, Parallel CMOS

Analog input BW (MHz)

450

Features

Low Power

Rating

Catalog

Peak-to-peak input voltage range (V)

2

Power consumption (typ) (mW)

740

Architecture

Pipeline

SNR (dB)

67.2

ENOB (Bits)

10.8

SFDR (dB)

89

Operating temperature range (°C)

-40 to 85

Input buffer

No

VQFN (RGC)

64

81 mm² (9 mm × 9 mm)

Maximum Sample Rate: 125 MSPS
11-Bit Resolution With No Missing Codes
84 dBc SFDR at Fin = 50 MHz
67.1 dBFS SNR at Fin = 50 MHz
92 dB Crosstalk
Parallel CMOS and DDR LVDS Output Options
3.5 dB Coarse Gain and Programmable Fine Gain
up to 6 dB for SNR/SFDR Trade-Off
Digital Processing Block With:
- Offset Correction
- Fine Gain Correction, in Steps of 0.05 dB
- Decimation by 2/4/8
- Built-in and Custom Programmable 24-Tap Low/High/
  Band Pass Filters
Supports Sine, LVPECL, LVDS & LVCMOS Clocks & Amplitude
Down to 400 mV_PP
Clock Duty Cycle Stabilizer
Internal Reference; Supports External Reference also
64-QFN Package (9mm × 9mm)
Pin Compatible 14-bit and 12-bit Family (ADS62P4X/ADS62P2X)

Maximum Sample Rate: 125 MSPS
11-Bit Resolution With No Missing Codes
84 dBc SFDR at Fin = 50 MHz
67.1 dBFS SNR at Fin = 50 MHz
92 dB Crosstalk
Parallel CMOS and DDR LVDS Output Options
3.5 dB Coarse Gain and Programmable Fine Gain
up to 6 dB for SNR/SFDR Trade-Off
Digital Processing Block With:
- Offset Correction
- Fine Gain Correction, in Steps of 0.05 dB
- Decimation by 2/4/8
- Built-in and Custom Programmable 24-Tap Low/High/
  Band Pass Filters
Supports Sine, LVPECL, LVDS & LVCMOS Clocks & Amplitude
Down to 400 mV_PP
Clock Duty Cycle Stabilizer
Internal Reference; Supports External Reference also
64-QFN Package (9mm × 9mm)
Pin Compatible 14-bit and 12-bit Family (ADS62P4X/ADS62P2X)

ADS62P15 is a dual channel 11-bit A/D converter with maximum sample rates up to 125 MSPS. It combines high performance and low power consumption in a compact 64 QFN package. Using an internal sample and hold and low jitter clock buffer, the ADC supports high SNR and high SFDR at high input frequencies. It has coarse and fine gain options that can be used to improve SFDR performance at lower full-scale input ranges.

ADS62P15 includes a digital processing block that consists of several useful and commonly used digital functions such as ADC offset correction, fine gain correction (in steps of 0.05 dB), decimation by 2,4,8 and in-built and custom programmable filters. By default, the digital processing block is bypassed, and its functions are disabled.

Two output interface options exist – parallel CMOS and DDR LVDS (Double Data Rate). ADS62P15 includes internal references while traditional reference pins and associated decoupling capacitors have been eliminated. Nevertheless, the device can also be driven with an external reference. The device is specified over the industrial temperature range (–40°C to 85°C).

ADS62P15 is a dual channel 11-bit A/D converter with maximum sample rates up to 125 MSPS. It combines high performance and low power consumption in a compact 64 QFN package. Using an internal sample and hold and low jitter clock buffer, the ADC supports high SNR and high SFDR at high input frequencies. It has coarse and fine gain options that can be used to improve SFDR performance at lower full-scale input ranges.

ADS62P15 includes a digital processing block that consists of several useful and commonly used digital functions such as ADC offset correction, fine gain correction (in steps of 0.05 dB), decimation by 2,4,8 and in-built and custom programmable filters. By default, the digital processing block is bypassed, and its functions are disabled.

Two output interface options exist – parallel CMOS and DDR LVDS (Double Data Rate). ADS62P15 includes internal references while traditional reference pins and associated decoupling capacitors have been eliminated. Nevertheless, the device can also be driven with an external reference. The device is specified over the industrial temperature range (–40°C to 85°C).

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Documentación técnica

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Ver todo 11

Documentación principal	Tipo	Título
*	Hoja de datos	Dual Channel 11-Bits 125-MSPS ADC w/parallel CMOS / DDR LVDS Outputs datasheet (Rev. C)	9/02/2012
	Nota sobre la aplicación	Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)	22/05/2015
	Nota sobre la aplicación	Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)	19/07/2013
	Nota sobre la aplicación	Band-Pass Filter Design Techniques for High-Speed ADCs	27/02/2012
	Nota sobre la aplicación	Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)	10/09/2010
	Nota sobre la aplicación	Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio	28/04/2009
	Guía del usuario	ADS62PxxEVM Quick Start Guide (Rev C Board) (Rev. A)	2/04/2009
	Nota sobre la aplicación	CDCE62005 as Clock Solution for High-Speed ADCs	4/09/2008
	Nota sobre la aplicación	CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters	8/06/2008
	Nota sobre la aplicación	Phase Noise Performance and Jitter Cleaning Ability of CDCE72010	2/06/2008
	Nota sobre la aplicación	QFN Layout Guidelines	28/07/2006

Diseño y desarrollo

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