AM1705

ACTIVO

Procesador Sitara: Arm9, SDRAM, Ethernet

Detalles del producto

CPU 1 Arm9 Frequency (MHz) 375, 456 Protocols Ethernet Hardware accelerators Programable real-time unit Operating system Linux, RTOS Security Device attestation & anti-counterfeit, Secure storage Rating Catalog Power supply solution TPS650061 Operating temperature range (°C) -40 to 105
CPU 1 Arm9 Frequency (MHz) 375, 456 Protocols Ethernet Hardware accelerators Programable real-time unit Operating system Linux, RTOS Security Device attestation & anti-counterfeit, Secure storage Rating Catalog Power supply solution TPS650061 Operating temperature range (°C) -40 to 105
HLQFP (PTP) 176 676 mm² (26 mm × 26 mm)
  • 375- and 456-MHz ARM926EJ-S™ RISC Core
    • 32-Bit and 16-Bit (Thumb®) Instructions
    • Single-Cycle MAC
    • ARM Jazelle® Technology
    • Embedded ICE-RT™ for Real-Time Debug
  • ARM9 Memory Architecture
    • 16KB of Instruction Cache
    • 16KB of Data Cache
    • 8KB of RAM (Vector Table)
    • 64KB of ROM
  • Enhanced Direct Memory Access Controller 3 (EDMA3):
    • 2 Transfer Controllers
    • 32 Independent DMA Channels
    • 8 Quick DMA Channels
    • Programmable Transfer Burst Size
  • 128KB of RAM Memory
  • 3.3-V LVCMOS I/Os (Except for USB Interface)
  • Two External Memory Interfaces:
    • EMIFA
      • NOR (8-Bit-Wide Data)
      • NAND (8-Bit-Wide Data)
    • EMIFB
      • 16-Bit SDRAM With 128-MB Address Space
  • Three Configurable 16550-Type UART Modules:
    • UART0 With Modem Control Signals
    • 16-Byte FIFO
    • 16x or 13x Oversampling Option
    • Autoflow Control Signals (CTS, RTS) on UART0 Only
  • Two Serial Peripheral Interfaces (SPIs) Each With One Chip Select
  • Programmable Real-Time Unit Subsystem (PRUSS)
    • Two Independent Programmable Real-Time Unit (PRU) Cores
      • 32-Bit Load-Store RISC Architecture
      • 4KB of Instruction RAM per Core
      • 512 Bytes of Data RAM per Core
      • PRUSS can be Disabled Through Software to Save Power
    • Standard Power-Management Mechanism
      • Clock Gating
      • Entire Subsystem Under a Single PSC Clock Gating Domain
    • Dedicated Interrupt Controller
    • Dedicated Switched Central Resource
  • Multimedia Card (MMC)/Secure Digital (SD) Card Interface With Secure Data I/O (SDIO)
  • Two Master and Slave Inter-Integrated Circuit (I2C Bus™)
  • USB 2.0 OTG Port With Integrated PHY (USB0)
    • USB 2.0 Full-Speed Client
    • USB 2.0 Full- and Low-Speed Host
    • End Point 0 (Control)
    • End Points 1, 2, 3, and 4 (Control, Bulk, Interrupt, or ISOC) RX and TX
  • Two Multichannel Audio Serial Ports (McASPs):
    • Six Clock Zones and 28 Serial Data Pins
    • Supports TDM, I2S, and Similar Formats
    • FIFO Buffers for Transmit and Receive
  • 10/100 Mbps Ethernet MAC (EMAC):
    • IEEE 802.3 Compliant (3.3-V I/O Only)
    • RMII Media-Independent Interface
    • Management Data I/O (MDIO) Module
  • One 64-Bit General-Purpose Timer (Configurable as Two 32-Bit Timers)
  • One 64-Bit General-Purpose Watchdog Timer (Configurable as Two 32-Bit General-Purpose Timers)
  • Three Enhanced Pulse Width Modulators (eHRPWMs):
    • Dedicated 16-Bit Time-Base Counter With Period and Frequency Control
    • 6 Single-Edge, 6 Dual-Edge Symmetric, or 3 Dual-Edge Asymmetric Outputs
    • Dead-Band Generation
    • PWM Chopping by High-Frequency Carrier
    • Trip Zone Input
  • Three 32-Bit Enhanced Capture (eCAP) Modules:
    • Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) Outputs
    • Single-Shot Capture of up to Four Event Timestamps
  • Two 32-Bit Enhanced Quadrature Encoder Pulse (eQEP) Modules
  • 176-Pin PowerPAD™ Plastic Quad Flat Pack [PTP suffix], 0.5-mm Pin Pitch
  • Commercial, Industrial, or Extended Temperature

All trademarks are the property of their respective owners.

  • 375- and 456-MHz ARM926EJ-S™ RISC Core
    • 32-Bit and 16-Bit (Thumb®) Instructions
    • Single-Cycle MAC
    • ARM Jazelle® Technology
    • Embedded ICE-RT™ for Real-Time Debug
  • ARM9 Memory Architecture
    • 16KB of Instruction Cache
    • 16KB of Data Cache
    • 8KB of RAM (Vector Table)
    • 64KB of ROM
  • Enhanced Direct Memory Access Controller 3 (EDMA3):
    • 2 Transfer Controllers
    • 32 Independent DMA Channels
    • 8 Quick DMA Channels
    • Programmable Transfer Burst Size
  • 128KB of RAM Memory
  • 3.3-V LVCMOS I/Os (Except for USB Interface)
  • Two External Memory Interfaces:
    • EMIFA
      • NOR (8-Bit-Wide Data)
      • NAND (8-Bit-Wide Data)
    • EMIFB
      • 16-Bit SDRAM With 128-MB Address Space
  • Three Configurable 16550-Type UART Modules:
    • UART0 With Modem Control Signals
    • 16-Byte FIFO
    • 16x or 13x Oversampling Option
    • Autoflow Control Signals (CTS, RTS) on UART0 Only
  • Two Serial Peripheral Interfaces (SPIs) Each With One Chip Select
  • Programmable Real-Time Unit Subsystem (PRUSS)
    • Two Independent Programmable Real-Time Unit (PRU) Cores
      • 32-Bit Load-Store RISC Architecture
      • 4KB of Instruction RAM per Core
      • 512 Bytes of Data RAM per Core
      • PRUSS can be Disabled Through Software to Save Power
    • Standard Power-Management Mechanism
      • Clock Gating
      • Entire Subsystem Under a Single PSC Clock Gating Domain
    • Dedicated Interrupt Controller
    • Dedicated Switched Central Resource
  • Multimedia Card (MMC)/Secure Digital (SD) Card Interface With Secure Data I/O (SDIO)
  • Two Master and Slave Inter-Integrated Circuit (I2C Bus™)
  • USB 2.0 OTG Port With Integrated PHY (USB0)
    • USB 2.0 Full-Speed Client
    • USB 2.0 Full- and Low-Speed Host
    • End Point 0 (Control)
    • End Points 1, 2, 3, and 4 (Control, Bulk, Interrupt, or ISOC) RX and TX
  • Two Multichannel Audio Serial Ports (McASPs):
    • Six Clock Zones and 28 Serial Data Pins
    • Supports TDM, I2S, and Similar Formats
    • FIFO Buffers for Transmit and Receive
  • 10/100 Mbps Ethernet MAC (EMAC):
    • IEEE 802.3 Compliant (3.3-V I/O Only)
    • RMII Media-Independent Interface
    • Management Data I/O (MDIO) Module
  • One 64-Bit General-Purpose Timer (Configurable as Two 32-Bit Timers)
  • One 64-Bit General-Purpose Watchdog Timer (Configurable as Two 32-Bit General-Purpose Timers)
  • Three Enhanced Pulse Width Modulators (eHRPWMs):
    • Dedicated 16-Bit Time-Base Counter With Period and Frequency Control
    • 6 Single-Edge, 6 Dual-Edge Symmetric, or 3 Dual-Edge Asymmetric Outputs
    • Dead-Band Generation
    • PWM Chopping by High-Frequency Carrier
    • Trip Zone Input
  • Three 32-Bit Enhanced Capture (eCAP) Modules:
    • Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) Outputs
    • Single-Shot Capture of up to Four Event Timestamps
  • Two 32-Bit Enhanced Quadrature Encoder Pulse (eQEP) Modules
  • 176-Pin PowerPAD™ Plastic Quad Flat Pack [PTP suffix], 0.5-mm Pin Pitch
  • Commercial, Industrial, or Extended Temperature

All trademarks are the property of their respective owners.

The AM1705 is a low-power ARM microprocessor based on an ARM926EJ-S.

The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices with robust operating systems, rich user interfaces, and high processor performance through the maximum flexibility of a fully integrated, mixed processor solution.

The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-, 16-, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.

The ARM core has a coprocessor 15 (CP15), protection module, and data and program memory management units (MMUs) with table look-aside buffers. The ARM core has separate 16KB of instruction and 16-KB data caches. Both memory blocks are 4-way associative with virtual index virtual tag (VIVT). The ARM core also has 8KB of RAM (Vector Table) and 64KB of ROM.

The peripheral set includes: a 10/100 Mbps Ethernet MAC (EMAC) with a management data input/output (MDIO) module; two I2C Bus interfaces; three multichannel audio serial ports (McASPs) with serializers and FIFO buffers; two 64-bit general-purpose timers each configurable (one configurable as watchdog); up to 8 banks of 16 pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; three UART interfaces (one with both RTS and CTS); three enhanced high-resolution pulse width modulator (eHRPWM) peripherals; three 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; two 32-bit enhanced quadrature encoded pulse (eQEP) peripherals; and 2 external memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals, and a higher speed memory interface (EMIFB) for SDRAM.

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the device and the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbps and 100 Mbps in either half- or full-duplex mode. Additionally, an MDIO interface is available for PHY configuration.

The I2C, SPI, and USB2.0 ports allow the device to easily control peripheral devices and/or communicate with host processors.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each peripheral, see the related sections later in this document and the associated peripheral reference guides.

The device has a complete set of development tools for the ARM processor. These tools include C compilers and a Windows® debugger interface for visibility into source code execution.

The AM1705 is a low-power ARM microprocessor based on an ARM926EJ-S.

The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices with robust operating systems, rich user interfaces, and high processor performance through the maximum flexibility of a fully integrated, mixed processor solution.

The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-, 16-, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.

The ARM core has a coprocessor 15 (CP15), protection module, and data and program memory management units (MMUs) with table look-aside buffers. The ARM core has separate 16KB of instruction and 16-KB data caches. Both memory blocks are 4-way associative with virtual index virtual tag (VIVT). The ARM core also has 8KB of RAM (Vector Table) and 64KB of ROM.

The peripheral set includes: a 10/100 Mbps Ethernet MAC (EMAC) with a management data input/output (MDIO) module; two I2C Bus interfaces; three multichannel audio serial ports (McASPs) with serializers and FIFO buffers; two 64-bit general-purpose timers each configurable (one configurable as watchdog); up to 8 banks of 16 pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; three UART interfaces (one with both RTS and CTS); three enhanced high-resolution pulse width modulator (eHRPWM) peripherals; three 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; two 32-bit enhanced quadrature encoded pulse (eQEP) peripherals; and 2 external memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals, and a higher speed memory interface (EMIFB) for SDRAM.

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the device and the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbps and 100 Mbps in either half- or full-duplex mode. Additionally, an MDIO interface is available for PHY configuration.

The I2C, SPI, and USB2.0 ports allow the device to easily control peripheral devices and/or communicate with host processors.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each peripheral, see the related sections later in this document and the associated peripheral reference guides.

The device has a complete set of development tools for the ARM processor. These tools include C compilers and a Windows® debugger interface for visibility into source code execution.

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Documentación técnica

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Documentación principal Tipo Título Opciones de formato Descargar la versión más reciente en inglés Fecha
* Hoja de datos AM1705 ARM® Microprocessor datasheet (Rev. F) PDF | HTML 31/01/2017
* Guía del usuario AM1705 ARM Microprocessor Technical Reference Manual (Rev. D) 21/09/2016
* Errata AM1705 ARM Microprocessor Silicon Errata (Silicon Revisions 3.0, 2.1, and 2.0) (Rev. E) 17/06/2014
Guía del usuario ARM Optimizing C/C++ Compiler v20.2.0.LTS User's Guide (Rev. W) PDF | HTML 30/03/2023
Guía del usuario ARM Assembly Language Tools v20.2.0.LTS User's Guide (Rev. Z) PDF | HTML 30/03/2023
Guía del usuario SYS/BIOS (TI-RTOS Kernel) User's Guide (Rev. V) 1/06/2020
Nota sobre la aplicación General Hardware Design/BGA PCB Design/BGA PDF | HTML 22/02/2019
Nota sobre la aplicación OMAP-L13x / C674x / AM1x schematic review guidelines PDF | HTML 14/02/2019
Guía del usuario How-To and Troubleshooting Guide for PRU-ICSS PROFIBUS 24/09/2018
Nota sobre la aplicación Using the AM17xx Bootloader (Rev. C) 31/05/2012
Nota sobre la aplicación Powering the AM1705 and AM1707 With the TPS650061 (Rev. A) 18/10/2011
Nota sobre la aplicación AM17x Power Consumption Summary 30/06/2010
Nota sobre la aplicación AM17xx Pin Multiplexing Utility 1/03/2010

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Sonda de depuración

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El XDS200 es una sonda de depuración (emulador) que se utiliza para depurar dispositivos integrados de TI. Para la mayoría de los dispositivos, se recomienda utilizar el XDS110 (www.ti.com/tool/TMDSEMU110-U), que es más nuevo y de menor costo. El XDS200 es compatible con una amplia variedad de (...)

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Sonda de depuración

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El XDS560v2 es el modelo de mayor rendimiento de la familia de sondas de depuración XDS560™ y es compatible tanto con el estándar JTAG tradicional (IEEE 1149.1) como con cJTAG (IEEE 1149.7).  Tenga en cuenta que no es compatible con la depuración por cable serie (SWD).

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Sonda de depuración

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The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

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Kit de desarrollo de software (SDK)

LINUXEZSDK-SITARA — Kit de desarrollo de software Linux EZ (EZSDK) para procesadores Sitara™

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IDE, configuración, compilador o depurador

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Modelo de simulación

AM1705 PTP IBIS Model (Rev. A)

SPRM491A.ZIP (109 KB) - Modelo IBIS
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Diseño de referencia

PR1061 — Alimentación de AM1705 y AM1707 con TPS650061

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Pedidos y calidad

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Soporte y capacitación

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