CD4002B

ACTIVO

Puertas NOR de 2 canales, 4 entradas, 3 V a 18 V

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Hoja de datos

document-pdfAcrobat CD4001B, CD4002B, CD4025B Types datasheet (Rev. C) (Inglés)

CD4002B

ACTIVO

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Detalles del producto

Technology family

CD4000

Number of channels

2

Inputs per channel

4

IOL (max) (mA)

6.8

IOH (max) (mA)

-6.8

Output type

Push-Pull

Input type

Standard CMOS

Features

Standard speed (tpd > 50ns)

Data rate (max) (Mbps)

8

Rating

Catalog

Operating temperature range (°C)

-55 to 125

Technology family

CD4000

Number of channels

2

Inputs per channel

4

IOL (max) (mA)

6.8

IOH (max) (mA)

-6.8

Output type

Push-Pull

Input type

Standard CMOS

Features

Standard speed (tpd > 50ns)

Data rate (max) (Mbps)

8

Rating

Catalog

Operating temperature range (°C)

-55 to 125

SOIC (D)

14

51.9 mm² (8.65 mm × 6 mm)

TSSOP (PW)

14

32 mm² (5 mm × 6.4 mm)

SOP (NS)

14

79.56 mm² (10.2 mm × 7.8 mm)

PDIP (N)

14

181.42 mm² (19.3 mm × 9.4 mm)

Propagation delay time = 60 ns (typ.) at C_L = 50 pF, V_DD = 10 V
Buffered inputs and outputs
Standardized symmetrical output characteristics
100% tested for maximum quiescent current at 20 V
5-V, 10-V, and 15-V parametric ratings
Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
Noise margin (over full package temperature range):
     1 V at V_DD = 5 V
     2 V at V_DD = 10 V
  2.5 V at V_DD = 15 V
Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"

Data sheet acquired from Harris Semiconductor

Propagation delay time = 60 ns (typ.) at C_L = 50 pF, V_DD = 10 V
Buffered inputs and outputs
Standardized symmetrical output characteristics
100% tested for maximum quiescent current at 20 V
5-V, 10-V, and 15-V parametric ratings
Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
Noise margin (over full package temperature range):
     1 V at V_DD = 5 V
     2 V at V_DD = 10 V
  2.5 V at V_DD = 15 V
Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"

Data sheet acquired from Harris Semiconductor

CD4001B, CD4002B, and CD4025B NOR gates provide the system designer with direct implementation of the NOR function and supplement the existing family of CMOS gates. All inputs and outputs are buffered.

The CD4001B, CD4002B, and CD4025B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).

CD4001B, CD4002B, and CD4025B NOR gates provide the system designer with direct implementation of the NOR function and supplement the existing family of CMOS gates. All inputs and outputs are buffered.

The CD4001B, CD4002B, and CD4025B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).

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Documentación principal	Tipo	Título	Opciones de formato	Descargar la versión más reciente en inglés		Fecha
*	Hoja de datos	CD4001B, CD4002B, CD4025B Types datasheet (Rev. C)			21/08/2003

CD4002B

Puertas NOR de 2 canales, 4 entradas, 3 V a 18 V

CD4002B

Detalles del producto

Documentación técnica

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