CD4012B

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Puertas NAND de 2 canales, 4 entradas, 3 V a 18 V

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document-pdfAcrobat CD4011B, CD4012B, CD4023B TYPES datasheet (Rev. D) (Inglés)

CD4012B

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Detalles del producto

Technology family

CD4000

Supply voltage (min) (V)

3

Supply voltage (max) (V)

18

Number of channels

2

Inputs per channel

4

IOL (max) (mA)

6.8

IOH (max) (mA)

-6.8

Input type

Standard CMOS

Output type

Push-Pull

Features

Standard speed (tpd > 50ns)

Data rate (max) (Mbps)

8

Rating

Catalog

Operating temperature range (°C)

-55 to 125

Technology family

CD4000

Supply voltage (min) (V)

3

Supply voltage (max) (V)

18

Number of channels

2

Inputs per channel

4

IOL (max) (mA)

6.8

IOH (max) (mA)

-6.8

Input type

Standard CMOS

Output type

Push-Pull

Features

Standard speed (tpd > 50ns)

Data rate (max) (Mbps)

8

Rating

Catalog

Operating temperature range (°C)

-55 to 125

PDIP (N)

14

181.42 mm² 19.3 x 9.4

SOIC (D)

14

51.9 mm² 8.65 x 6

SOP (NS)

14

79.56 mm² 10.2 x 7.8

TSSOP (PW)

14

32 mm² 5 x 6.4

Propagation delay time = 60 ns (typ.) at C_L = 50 pF, V_DD = 10 V
Buffered inputs and outputs
Standardized symmetrical output characteristics
Maximum input current of 1 µA at 18 V over-full package temperature range; 100 nA at 18 V and 25°C
100% tested for quiescent current at 20 V
5-V, 10-V, and 15-V parametric ratings
Noise margin (over full package temperature range:
    1 V at V_DD = 5 V
    2 V at V_DD = 10 V
    2.5 at V_DD = 15 V
Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of "B" Series CMOS Devices"

Quad 2 Input—CD4011B
Dual 4 Input—CD4012B
Triple 3 Input—CD4023B
Data sheet acquired from Harris Semiconductor.

Propagation delay time = 60 ns (typ.) at C_L = 50 pF, V_DD = 10 V
Buffered inputs and outputs
Standardized symmetrical output characteristics
Maximum input current of 1 µA at 18 V over-full package temperature range; 100 nA at 18 V and 25°C
100% tested for quiescent current at 20 V
5-V, 10-V, and 15-V parametric ratings
Noise margin (over full package temperature range:
    1 V at V_DD = 5 V
    2 V at V_DD = 10 V
    2.5 at V_DD = 15 V
Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of "B" Series CMOS Devices"

Quad 2 Input—CD4011B
Dual 4 Input—CD4012B
Triple 3 Input—CD4023B
Data sheet acquired from Harris Semiconductor.

CD4011B, CD4012B, and CD4023B NAND gates provide the system designer with direct implementation of the NAND function and supplement the existing family of CMOS gates. All inputs and outputs are buffered.

The CD4011B, CD4012B, and CD4023B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PWR suffix). The CD4011B and CD4023B types also are supplied in 14-lead thin shrink small-outline packages (PW suffix).

CD4011B, CD4012B, and CD4023B NAND gates provide the system designer with direct implementation of the NAND function and supplement the existing family of CMOS gates. All inputs and outputs are buffered.

The CD4011B, CD4012B, and CD4023B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PWR suffix). The CD4011B and CD4023B types also are supplied in 14-lead thin shrink small-outline packages (PW suffix).

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SN74LVC2G00

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	Tipo	Título		Fecha
*	Data sheet	CD4011B, CD4012B, CD4023B TYPES datasheet (Rev. D)		21 ago 2003

CD4012B

Puertas NAND de 2 canales, 4 entradas, 3 V a 18 V

CD4012B

Detalles del producto

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