CD4068B

ACTIVO

Puerta NAND/AND de 8 entradas CMOS

Haga su pedido ahora

Hoja de datos

document-pdfAcrobat CD4068B TYPES datasheet (Rev. C) (Inglés)

CD4068B

ACTIVO

Hoja de datos

Haga su pedido ahora

Detalles del producto

Technology family

CD4000

Number of channels

1

Inputs per channel

8

IOL (max) (mA)

6.8

IOH (max) (mA)

-6.8

Input type

Standard CMOS

Output type

Push-Pull

Features

Standard speed (tpd > 50ns)

Data rate (max) (Mbps)

8

Rating

Catalog

Operating temperature range (°C)

-55 to 125

Technology family

CD4000

Number of channels

1

Inputs per channel

8

IOL (max) (mA)

6.8

IOH (max) (mA)

-6.8

Input type

Standard CMOS

Output type

Push-Pull

Features

Standard speed (tpd > 50ns)

Data rate (max) (Mbps)

8

Rating

Catalog

Operating temperature range (°C)

-55 to 125

TSSOP (PW)

14

32 mm² (5 mm × 6.4 mm)

PDIP (N)

14

181.42 mm² (19.3 mm × 9.4 mm)

SOP (NS)

14

79.56 mm² (10.2 mm × 7.8 mm)

SOIC (D)

14

51.9 mm² (8.65 mm × 6 mm)

Medium Speed Operation:
t_PHL, t_PLH=75 ns (typ.) at V_DD = 10 V
Buffered inputs and outputs
5-V, 10-V, and 15-V parametric ratings
Standardized symmetrical output characteristics
100% tested for quiescent current at 20 V
Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
Noise margin (over full package-temperature range) =
     1 V at V_DD = 5 V
     2 V at V_DD = 10 V
  2.5 V at V_DD = 15 V
Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"

Data sheet acquired from Harris Semiconductor

Medium Speed Operation:
t_PHL, t_PLH=75 ns (typ.) at V_DD = 10 V
Buffered inputs and outputs
5-V, 10-V, and 15-V parametric ratings
Standardized symmetrical output characteristics
100% tested for quiescent current at 20 V
Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
Noise margin (over full package-temperature range) =
     1 V at V_DD = 5 V
     2 V at V_DD = 10 V
  2.5 V at V_DD = 15 V
Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"

Data sheet acquired from Harris Semiconductor

CD4068B NAND/AND gate provides the system designer with direct implementation of the positive-logic 8-input NAND and AND functions and supplements the existing family of CMOS gates.

The CD4068B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).

CD4068B NAND/AND gate provides the system designer with direct implementation of the positive-logic 8-input NAND and AND functions and supplements the existing family of CMOS gates.

The CD4068B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).

filter

Buscar otro/a Compuertas combinadas

Descargar

Documentación técnica

No se encontraron resultados. Borre su búsqueda y vuelva a intentarlo.

Ver todo 1

Documentación principal	Tipo	Título	Opciones de formato	Descargar la versión más reciente en inglés	Fecha
*	Hoja de datos	CD4068B TYPES datasheet (Rev. C)			21/08/2003

CD4068B

Puerta NAND/AND de 8 entradas CMOS

CD4068B

Detalles del producto

Documentación técnica

Pedidos y calidad

Soporte y capacitación

Foros de TI E2E™ con asistencia técnica de los ingenieros de TI