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Biestables tipo D

SN54LS273-SP

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QML-V, Octal D-type Flip-Flop With Clear

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Hoja de datos

SN54LS273-SP

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Detalles del producto

Number of channels 8 Technology family LS Input type Bipolar Output type Push-Pull Clock frequency (max) (MHz) 35 IOL (max) (mA) 8 IOH (max) (mA) -0.4 Supply current (max) (µA) 27000 Features High speed (tpd 10-50ns) Operating temperature range (°C) -55 to 125 Rating Space
Number of channels 8 Technology family LS Input type Bipolar Output type Push-Pull Clock frequency (max) (MHz) 35 IOL (max) (mA) 8 IOH (max) (mA) -0.4 Supply current (max) (µA) 27000 Features High speed (tpd 10-50ns) Operating temperature range (°C) -55 to 125 Rating Space
CDIP (J) 20 167.464 mm² (— mm × — mm)
  • Contains Eight Flip-Flops With Single-Rail Outputs
  • Buffered Clock and Direct Clear Inputs
  • Individual Data Input to Each Flip-Flop
  • Applications Include:
    • Buffer/Storage Registers
    • Shift Registers
    • Pattern Generators
  • Contains Eight Flip-Flops With Single-Rail Outputs
  • Buffered Clock and Direct Clear Inputs
  • Individual Data Input to Each Flip-Flop
  • Applications Include:
    • Buffer/Storage Registers
    • Shift Registers
    • Pattern Generators

These monolithic, positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic with a direct clear input.

Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the output.

These flip-flops are guaranteed to respond to clock frequencies ranging form 0 to 30 megahertz while maximum clock frequency is typically 40 megahertz. Typical power dissipation is 39 milliwatts per flip-flop for the ´273 and 10 milliwatts for the ´LS273.

 

 

 

These monolithic, positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic with a direct clear input.

Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the output.

These flip-flops are guaranteed to respond to clock frequencies ranging form 0 to 30 megahertz while maximum clock frequency is typically 40 megahertz. Typical power dissipation is 39 milliwatts per flip-flop for the ´273 and 10 milliwatts for the ´LS273.

 

 

 
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Documentación principal Tipo Título Opciones de formato Descargar la versión más reciente en inglés Fecha
* Hoja de datos Octal D-Type Flip-Flop With Clear--SN54273, SN54LS273, SN74273, SN74LS273 datasheet 1/03/1988
* SMD SN54LS273-SP SMD 5962-78010 8/07/2016

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