SN74ALVCH16827

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Búferes de 20 canales, 1.65 V a 3.6 V con retención de bus y salidas de 3 estados

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Hoja de datos

document-pdfAcrobat SN74ALVCH16827 datasheet (Rev. D) (Inglés)

SN74ALVCH16827

ACTIVO

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Detalles del producto

Technology family

ALVC

Number of channels

20

IOL (max) (mA)

24

Supply current (max) (µA)

40

IOH (max) (mA)

-24

Input type

Standard CMOS

Output type

3-State

Features

Balanced outputs, Bus-hold, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Technology family

ALVC

Number of channels

20

IOL (max) (mA)

24

Supply current (max) (µA)

40

IOH (max) (mA)

-24

Input type

Standard CMOS

Output type

3-State

Features

Balanced outputs, Bus-hold, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 85

TSSOP (DGG)

56

113.4 mm² (14 mm × 8.1 mm)

SSOP (DL)

56

190.647 mm² (18.42 mm × 10.35 mm)

Member of the Texas Instruments Widebus™ Family
EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process
ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA Per JESD 17
Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages

Widebus, EPIC are trademarks of Texas Instruments.

Member of the Texas Instruments Widebus™ Family
EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process
ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA Per JESD 17
Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages

Widebus, EPIC are trademarks of Texas Instruments.

This 20-bit noninverting buffer/driver is designed for 1.65-V to 3.6-V V_CC operation.

The SN74ALVCH16827 is composed of two 10-bit sections with separate output-enable signals. For either 10-bit buffer section, the two output-enable (1OE1\ and 1OE2\ or 2OE1\ and 2OE2\) inputs must both be low for the corresponding Y outputs to be active. If either output-enable input is high, the outputs of that 10-bit buffer section are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN74ALVCH16827 is characterized for operation from -40°C to 85°C.

This 20-bit noninverting buffer/driver is designed for 1.65-V to 3.6-V V_CC operation.

The SN74ALVCH16827 is composed of two 10-bit sections with separate output-enable signals. For either 10-bit buffer section, the two output-enable (1OE1\ and 1OE2\ or 2OE1\ and 2OE2\) inputs must both be low for the corresponding Y outputs to be active. If either output-enable input is high, the outputs of that 10-bit buffer section are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN74ALVCH16827 is characterized for operation from -40°C to 85°C.

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SN74AVC16827

ACTIVO

Búferes de 20 canales, 1.2 V a 3.6 V con salidas de 3 estados Voltage range 0.9V to 3.6V, average propagation delay 2ns, average drive strength 12mA

Documentación técnica

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Ver todo 3

Documentación principal	Tipo	Título
*	Hoja de datos	SN74ALVCH16827 datasheet (Rev. D)	2/09/2004
	Nota sobre la aplicación	An Overview of Bus-Hold Circuit and the Applications (Rev. B)	17/09/2018
	Nota sobre la aplicación	Timing Differences of 10-pF Versus 50pF Loading	1/11/1996

Diseño y desarrollo

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