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UCC27524A-Q1

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UCC27624-Q1 ACTIVO Contr. puerta de lado bajo, doble canal, 5 A/5 A, autom., VDD de 30 V, UVLO de 4 V, bajo retardo de Next generation with better negative voltage handling and robustness and wider voltage range

UCC27524A-Q1

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Detalles del producto

Number of channels 2 Power switch GaNFET, IGBT, MOSFET Input supply voltage (min) (V) 4.5 Input supply voltage (max) (V) 18 Features Enable pin Operating temperature range (°C) -40 to 140 Rise time (ns) 7 Fall time (ns) 6 Propagation delay time (µs) 0.013 Input threshold CMOS, TTL Channel input logic Dual, Non-Inverting Input negative voltage (V) -5 Rating Automotive Undervoltage lockout (typ) (V) 4 Driver configuration Dual, Non-Inverting
Number of channels 2 Power switch GaNFET, IGBT, MOSFET Input supply voltage (min) (V) 4.5 Input supply voltage (max) (V) 18 Features Enable pin Operating temperature range (°C) -40 to 140 Rise time (ns) 7 Fall time (ns) 6 Propagation delay time (µs) 0.013 Input threshold CMOS, TTL Channel input logic Dual, Non-Inverting Input negative voltage (V) -5 Rating Automotive Undervoltage lockout (typ) (V) 4 Driver configuration Dual, Non-Inverting
SOIC (D) 8 29.4 mm² (4.9 mm × 6 mm) HVSSOP (DGN) 8 14.7 mm² (3 mm × 4.9 mm)
  • Qualified for automotive applications
  • AEC-Q100 qualified with the following results
    • Device temperature grade 1
  • Industry-standard pin out
  • Two independent gate-drive channels
  • 5A peak source and sink-drive current
  • Independent enable function for each output
  • TTL and CMOS-compatible logic threshold independent of supply voltage
  • Hysteretic-logic thresholds for high-noise immunity
  • Ability to handle negative voltages (–5V) at inputs
  • Inputs and enable pin-voltage levels not restricted by VDD pin bias supply voltage
  • 4.5V to 18V single-supply range
  • Outputs held low during VDD-UVLO, (ensures glitch-free operation at power-up and power-down)
  • Fast propagation delays (17ns typical)
  • Fast rise and fall times (6ns and 10ns typical)
  • 1ns typical delay matching between 2-channels
  • Ability to parallel two outputs for high-drive current
  • Outputs held in low when inputs are floating
  • SOIC-8 and VSSOP-8 PowerPad™ package options
  • Operating temperature range of –40°C to 150°C
  • Qualified for automotive applications
  • AEC-Q100 qualified with the following results
    • Device temperature grade 1
  • Industry-standard pin out
  • Two independent gate-drive channels
  • 5A peak source and sink-drive current
  • Independent enable function for each output
  • TTL and CMOS-compatible logic threshold independent of supply voltage
  • Hysteretic-logic thresholds for high-noise immunity
  • Ability to handle negative voltages (–5V) at inputs
  • Inputs and enable pin-voltage levels not restricted by VDD pin bias supply voltage
  • 4.5V to 18V single-supply range
  • Outputs held low during VDD-UVLO, (ensures glitch-free operation at power-up and power-down)
  • Fast propagation delays (17ns typical)
  • Fast rise and fall times (6ns and 10ns typical)
  • 1ns typical delay matching between 2-channels
  • Ability to parallel two outputs for high-drive current
  • Outputs held in low when inputs are floating
  • SOIC-8 and VSSOP-8 PowerPad™ package options
  • Operating temperature range of –40°C to 150°C

The UCC27524A-Q1 device is a dual-channel, high-speed, low-side, gate-driver device capable of effectively driving MOSFET and IGBT power switches. The UCC27524A-Q1 device is a variant of the UCC2752x family. The UCC27524A-Q1 device adds the ability to handle –5V directly at the input pins for increased robustness. The UCC27524A-Q1 device is a dual, non-inverting driver. Using a design that inherently minimizes shoot-through current, the UCC27524A-Q1 device is capable of delivering high-peak current pulses of up to 5A source and 5A sink into capacitive loads along with rail-to-rail drive capability and extremely small propagation delay (typically 17ns). In addition, the drivers feature matched, internal-propagation delays between the two channels which are very well suited for applications requiring dual-gate drives with critical timing, such as synchronous rectifiers. This also enables connecting two channels in parallel to effectively increase current-drive capability or driving two switches in parallel with a single input signal. The input pin thresholds are based on TTL and CMOS compatible low-voltage logic, which is fixed and independent of the VDD supply voltage. Wide hysteresis between the high and low thresholds offers excellent noise immunity.

For protection purposes, internal pull-up and pull-down resistors on the input pins of the UCC27524A-Q1 device ensure that outputs are held LOW when input pins are in floating condition. The UCC27524A-Q1 device features enable pins (ENA and ENB) to have better control of the operation of the driver applications. The pins are internally pulled up to VDD for active-high logic and are left open for standard operation.

The UCC27524A-Q1 devices is available in SOIC-8 (D) and VSSOP-PowerPAD-8 with exposed pad (DGN) packages.

The UCC27524A-Q1 device is a dual-channel, high-speed, low-side, gate-driver device capable of effectively driving MOSFET and IGBT power switches. The UCC27524A-Q1 device is a variant of the UCC2752x family. The UCC27524A-Q1 device adds the ability to handle –5V directly at the input pins for increased robustness. The UCC27524A-Q1 device is a dual, non-inverting driver. Using a design that inherently minimizes shoot-through current, the UCC27524A-Q1 device is capable of delivering high-peak current pulses of up to 5A source and 5A sink into capacitive loads along with rail-to-rail drive capability and extremely small propagation delay (typically 17ns). In addition, the drivers feature matched, internal-propagation delays between the two channels which are very well suited for applications requiring dual-gate drives with critical timing, such as synchronous rectifiers. This also enables connecting two channels in parallel to effectively increase current-drive capability or driving two switches in parallel with a single input signal. The input pin thresholds are based on TTL and CMOS compatible low-voltage logic, which is fixed and independent of the VDD supply voltage. Wide hysteresis between the high and low thresholds offers excellent noise immunity.

For protection purposes, internal pull-up and pull-down resistors on the input pins of the UCC27524A-Q1 device ensure that outputs are held LOW when input pins are in floating condition. The UCC27524A-Q1 device features enable pins (ENA and ENB) to have better control of the operation of the driver applications. The pins are internally pulled up to VDD for active-high logic and are left open for standard operation.

The UCC27524A-Q1 devices is available in SOIC-8 (D) and VSSOP-PowerPAD-8 with exposed pad (DGN) packages.
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Documentación técnica

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Documentación principal Tipo Título Opciones de formato Descargar la versión más reciente en inglés Fecha
* Hoja de datos UCC27524A-Q1 Dual 5A, High-Speed, Low-Side Gate Driver With Negative Input Voltage Capability datasheet (Rev. C) PDF | HTML 13/06/2024
Información sobre seguridad funcional UCC27524A-Q1 Functional Safety FIT Rate, FMD and Pin FMA (Rev. A) PDF | HTML 3/09/2024
Nota sobre la aplicación Why use a Gate Drive Transformer? PDF | HTML 4/03/2024
Nota sobre la aplicación Static Magnet Power Supply Design for Magnetic Resonance Imaging Application PDF | HTML 22/01/2024
Nota sobre la aplicación Review of Different Power Factor Correction (PFC) Topologies' Gate Driver Needs PDF | HTML 22/01/2024
Nota sobre la aplicación Benefits of a Compact, Powerful, and Robust Low-Side Gate Driver PDF | HTML 10/11/2021
Application brief External Gate Resistor Selection Guide (Rev. A) 28/02/2020
Application brief Understanding Peak IOH and IOL Currents (Rev. A) 28/02/2020
Nota sobre la aplicación Improving Efficiency of DC-DC Conversion through Layout 7/05/2019
Application brief How to overcome negative voltage transients on low-side gate drivers' inputs 18/01/2019
Application brief High-Side Cutoff Switches for High-Power Automotive Applications (Rev. A) 26/11/2018
Más documentación Fundamentals of MOSFET and IGBT Gate Driver Circuits (Replaces SLUP169) (Rev. A) 29/10/2018
Nota sobre la aplicación PFC Design Choice for On Board Charger Designs 24/05/2018
Informe Driving the future of HEV/EV with high-voltage solutions (Rev. B) 16/05/2018
Application brief Reducing Switching Losses in On-Board Chargers for Electric Vehicles 27/03/2018
Application brief Low-Side Gate Drivers With UVLO Versus BJT Totem-Pole 16/03/2018
Artículo técnico Are you on-board? Demystifying EV charging systems PDF | HTML 31/07/2017

Diseño y desarrollo

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