CD4001UB

アクティブ

4 チャネル、2 入力、3V ～ 18V NOR ゲート

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データシート

document-pdfAcrobat CD4001UB TYPES データシート (Rev. C) (英語)

CD4001UB

アクティブ

ご注文はこちら

製品詳細

Technology family

CD4000

Number of channels

Inputs per channel

IOL (max) (mA)

6.8

IOH (max) (mA)

-6.8

Output type

Push-Pull

Input type

Standard CMOS

Features

Standard speed (tpd > 50ns)

Data rate (max) (Mbps)

Rating

Catalog

Operating temperature range (°C)

-55 to 125

Technology family

CD4000

Number of channels

Inputs per channel

IOL (max) (mA)

6.8

IOH (max) (mA)

-6.8

Output type

Push-Pull

Input type

Standard CMOS

Features

Standard speed (tpd > 50ns)

Data rate (max) (Mbps)

Rating

Catalog

Operating temperature range (°C)

-55 to 125

TSSOP (PW)

32 mm² (5 mm × 6.4 mm)

SOIC (D)

51.9 mm² (8.65 mm × 6 mm)

PDIP (N)

181.42 mm² (19.3 mm × 9.4 mm)

Propagation delay time = 30 ns (typ.) at C_L = 50 pF, V_DD = 10 V
Standardized symmetrical output characteristics
100% tested for maximum quiescent current at 20 V
Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
5-V, 10-V, and 15-V parametric ratings

Data sheet acquired from Harris Semiconductor

Propagation delay time = 30 ns (typ.) at C_L = 50 pF, V_DD = 10 V
Standardized symmetrical output characteristics
100% tested for maximum quiescent current at 20 V
Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
5-V, 10-V, and 15-V parametric ratings

Data sheet acquired from Harris Semiconductor

CD4001UB quad 2-input NOR gate provides the system designer with direct implementation of the NOR function and supplements the existing family of CMOS gates.

The CD4001UB types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).

CD4001UB quad 2-input NOR gate provides the system designer with direct implementation of the NOR function and supplements the existing family of CMOS gates.

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