ホーム ロジックと電圧変換 フリップ フロップ、ラッチ、レジスタ D タイプ ラッチ
ホーム
ロジックと電圧変換
フリップ フロップ、ラッチ、レジスタ
D タイプ ラッチ

SN54ABT843

アクティブ

3 ステート出力、9 ビット バス インターフェイス D タイプ ラッチ

ご注文はこちら
データシート

SN54ABT843

アクティブ
データシート ご注文はこちら

製品詳細

Number of channels 9 Technology family ABT Input type TTL-Compatible CMOS Output type 3-State Clock frequency (max) (MHz) 150 IOL (max) (mA) 64 IOH (max) (mA) -32 Supply current (max) (µA) 34000 Features Flow-through pinout, Partial power down (Ioff), Power up 3-state, Very high speed (tpd 5-10ns) Operating temperature range (°C) -55 to 125 Rating Military
Number of channels 9 Technology family ABT Input type TTL-Compatible CMOS Output type 3-State Clock frequency (max) (MHz) 150 IOL (max) (mA) 64 IOH (max) (mA) -32 Supply current (max) (µA) 34000 Features Flow-through pinout, Partial power down (Ioff), Power up 3-state, Very high speed (tpd 5-10ns) Operating temperature range (°C) -55 to 125 Rating Military
CDIP (JT) 24 221.44 mm² (— mm × — mm)
  • State-of-the-Art EPIC-II BTM BiCMOS Design Significantly Reduces Power Dissipation
  • Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
  • Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C
  • High-Drive Outputs (-32-mA IOH, 64-mA IOL)
  • Package Options Include Plastic Small-Outline (DW) and Shrink Small-Outline (DB) Packages, Ceramic Chip Carriers (FK), Ceramic Flat (W) Package, and Plastic (NT) and Ceramic (JT) DIPs

    EPIC-IIB is a trademark of Texas Instruments Incorporated.
  • State-of-the-Art EPIC-II BTM BiCMOS Design Significantly Reduces Power Dissipation
  • Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
  • Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C
  • High-Drive Outputs (-32-mA IOH, 64-mA IOL)
  • Package Options Include Plastic Small-Outline (DW) and Shrink Small-Outline (DB) Packages, Ceramic Chip Carriers (FK), Ceramic Flat (W) Package, and Plastic (NT) and Ceramic (JT) DIPs

    EPIC-IIB is a trademark of Texas Instruments Incorporated.

The 'ABT843 9-bit latches are designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The nine transparent D-type latches provide true data at the outputs.

A buffered output-enable (OE\) input can be used to place the nine outputs in either a normal logic state (high or low logic levels) or a high-impedance state. The outputs are also in the high-impedance state during power-up and power-down conditions. The outputs remain in the high-impedance state while the device is powered down. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

OE\ does not affect the internal operations of the latch. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABT843 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT843 is characterized for operation from -40°C to 85°C.

The 'ABT843 9-bit latches are designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The nine transparent D-type latches provide true data at the outputs.

A buffered output-enable (OE\) input can be used to place the nine outputs in either a normal logic state (high or low logic levels) or a high-impedance state. The outputs are also in the high-impedance state during power-up and power-down conditions. The outputs remain in the high-impedance state while the device is powered down. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

OE\ does not affect the internal operations of the latch. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABT843 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT843 is characterized for operation from -40°C to 85°C.

filter その他の D タイプ ラッチ を検索
ダウンロード 字幕付きのビデオを表示 ビデオ

技術資料

結果が見つかりませんでした。検索条件をクリアしてから、再度検索を試してください。
3 をすべて表示
上位の文書 タイプ タイトル フォーマットオプション 最新の英語版をダウンロード 日付
* データシート 9-Bit Bus-Interface D-Type Latches With 3-State Outputs データシート (Rev. D) 1997/05/01
* SMD SN54ABT843 SMD 5962-95712 2016/06/21
アプリケーション・ノート Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 2022/12/15

設計と開発

その他のアイテムや必要なリソースを参照するには、以下のタイトルをクリックして詳細ページをご覧ください。

パッケージ ピン数 CAD シンボル、フットプリント、および 3D モデル
CDIP (JT) 24 Ultra Librarian
TI の評価基板に関する標準契約約款が適用されます。

購入と品質

サポートとトレーニング

TI E2E™ フォーラムでは、TI のエンジニアからの技術サポートを提供

投稿されたすべてのフォーラムトピック (英語) を表示

コンテンツは、TI 投稿者やコミュニティ投稿者によって「現状のまま」提供されるもので、TI による仕様の追加を意図するものではありません。使用条件をご確認ください。

TI 製品の品質、パッケージ、ご注文に関するお問い合わせは、TI サポートをご覧ください。​​​​​​​​​​​​​​

ビデオ