パッケージ情報
| パッケージ | ピン数 CDIP (JT) | 28 |
| 動作温度範囲 (℃) -55 to 125 |
| パッケージ数量 | キャリア 13 | TUBE |
SN54ABT8646 の特徴
- Members of the Texas Instruments SCOPE™ Family of Testability Products
- Compatible With the IEEE Standard 1149.1–1990 (JTAG) Test Access Port and Boundary-Scan Architecture
- Functionally Equivalent to ’F646 and ’ABT646 in the Normal-Function Mode
- SCOPE™ Instruction Set
- IEEE Standard 1149.1-1990 Required Instructions, Optional INTEST, CLAMP, and HIGHZ
- Parallel-Signature Analysis at Inputs With Masking Option
- Pseudorandom Pattern Generation From Outputs
- Sample Inputs/Toggle Outputs
- Binary Count From Outputs
- Even-Parity Opcodes
- Two Boundary-Scan Cells Per I/O for Greater Flexibility
- State-of-the-Art EPIC-IIB™ BiCMOS Design Significantly Reduces Power Dissipation
- Package Options Include Plastic Small-Outline (DW) and Shrink Small-Outline (DL) Packages, Ceramic Chip Carriers (FK), and Standard Ceramic DIPs (JT)
SCOPE and EPCI-IIB are trademarks of Texas Instruments.
SN54ABT8646 に関する概要
The ’ABT8646 and scan test devices with octal bus transceivers and registers are members of the Texas Instruments SCOPE™ testability integrated-circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.
In the normal mode, these devices are functionally equivalent to the ’F646 and ’ABT646 octal bus transceivers and registers. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating the TAP in normal mode does not affect the functional operation of the SCOPE™ octal bus transceivers and registers.
Transceiver function is controlled by output-enable (OE)\ and direction (DIR) inputs. When OE\ is low, the transceiver is active and operates in the A-to-B direction when DIR is high or in the B-to-A direction when DIR is low. When OE\ is high, both the A and B outputs are in the high-impedance state, effectively isolating both buses.
Data flow is controlled by clock (CLKAB and CLKBA) and select (SAB and SBA) inputs. Data on the A bus is clocked into the associated registers on the low-to-high transition of CLKAB. When SAB is low, real-time A data is selected for presentation to the B bus (transparent mode). When SAB is high, stored A data is selected for presentation to the B bus (registered mode). The function of the CLKBA and SBA inputs mirrors that of CLKAB and SAB, respectively. Figure 1 shows the four fundamental bus-management functions that can be performed with the ’ABT8646.
In the test mode, the normal operation of the SCOPE™ bus transceivers and registers is inhibited, and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry performs boundary-scan test operations as described in IEEE Standard 1149.1-1990.
Four dedicated test pins control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudorandom pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.
The SN54ABT8646 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74ABT8646 is characterized for operation from –40°C to 85°C.