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SN74ABT16543

アクティブ

3 ステート出力、16 ビット レジスタ トランシーバ

ご注文はこちら
データシート

SN74ABT16543

アクティブ
データシート ご注文はこちら

製品詳細

Number of channels 16 IOL (max) (mA) 64 IOH (max) (mA) -32 Input type TTL Output type TTL Features Over-voltage tolerant inputs, Partial power down (Ioff), Power up 3-state, Very high speed (tpd 5-10ns) Technology family ABT Rating Catalog Operating temperature range (°C) -40 to 85
Number of channels 16 IOL (max) (mA) 64 IOH (max) (mA) -32 Input type TTL Output type TTL Features Over-voltage tolerant inputs, Partial power down (Ioff), Power up 3-state, Very high speed (tpd 5-10ns) Technology family ABT Rating Catalog Operating temperature range (°C) -40 to 85
SSOP (DL) 56 190.647 mm² (18.42 mm × 10.35 mm) TSSOP (DGG) 56 113.4 mm² (14 mm × 8.1 mm)
  • Members of the Texas Instruments WidebusTM Family
  • State-of-the-Art EPIC-IIBTM BiCMOS Design Significantly Reduces Power Dissipation
  • Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
  • Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C
  • Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
  • Flow-Through Architecture Optimizes PCB Layout
  • High-Drive Outputs (-32-mA IOH, 64-mA IOL)
  • Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings

 

Widebus and EPIC-IIB are trademarks of Texas Instruments Incorporated.
  • Members of the Texas Instruments WidebusTM Family
  • State-of-the-Art EPIC-IIBTM BiCMOS Design Significantly Reduces Power Dissipation
  • Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
  • Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C
  • Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
  • Flow-Through Architecture Optimizes PCB Layout
  • High-Drive Outputs (-32-mA IOH, 64-mA IOL)
  • Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings

 

Widebus and EPIC-IIB are trademarks of Texas Instruments Incorporated.

The 'ABT16543 16-bit registered transceivers contain two sets of D-type latches for temporary storage of data flowing in either direction. The 'ABT16543 can be used as two 8-bit transceivers or one 16-bit transceiver. Separate latch-enable ( or) and output-enable ( or ) inputs are provided for each register to permit independent control in either direction of data flow.

The A-to-B enable () input must be low to enter data from A or to output data from B. If is low and is low, the A-to-B latches are transparent; a subsequent low-to-high transition of puts the A latches in the storage mode. With and both low, the 3-state B outputs are active and reflect the data present at the output of the A latches. Data flow from B to A is similar but requires using the,, and inputs.

To ensure the high-impedance state during power up or power down, should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABT16543 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT16543 is characterized for operation from -40°C to 85°C.

 

 

 

The 'ABT16543 16-bit registered transceivers contain two sets of D-type latches for temporary storage of data flowing in either direction. The 'ABT16543 can be used as two 8-bit transceivers or one 16-bit transceiver. Separate latch-enable ( or) and output-enable ( or ) inputs are provided for each register to permit independent control in either direction of data flow.

The A-to-B enable () input must be low to enter data from A or to output data from B. If is low and is low, the A-to-B latches are transparent; a subsequent low-to-high transition of puts the A latches in the storage mode. With and both low, the 3-state B outputs are active and reflect the data present at the output of the A latches. Data flow from B to A is similar but requires using the,, and inputs.

To ensure the high-impedance state during power up or power down, should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABT16543 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT16543 is characterized for operation from -40°C to 85°C.

 

 

 
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上位の文書 タイプ タイトル フォーマットオプション 最新の英語版をダウンロード 日付
* データシート 16-Bit Registered Transceivers With 3-State Outputs データシート (Rev. C) 1997/01/01

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シミュレーション・モデル

SN74ABT16543 IBIS Model (Rev. A)

SCBM015 (5 KB) - IBIS モデル
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SSOP (DL) 56 Ultra Librarian
TSSOP (DGG) 56 Ultra Librarian
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