SN74ABT646
- State-of-the-Art EPIC-IIBTM BiCMOS Design Significantly Reduces Power Dissipation
- ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
- Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
- Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C
- High-Drive Outputs (-32-mA IOH, 64-mA IOL)
- Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), and Plastic (NT) and Ceramic (JT) DIPs
EPIC-IIB is a trademark of Texas Instruments Incorporated.
These devices consist of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the ´ABT646.
Output-enable (
) and
direction-control (DIR) inputs are provided to control the
transceiver functions. In the transceiver mode, data present at the
high-impedance port may be stored in either register or in both.
The select-control (SAB and SBA) inputs can multiplex stored and
real-time (transparent mode) data. The direction control (DIR)
determines which bus will receive data when is low. In the isolation mode
( high), A data
may be stored in one register and/or B data may be stored in the
other register.
When an output function is disabled, the input function is still enabled and may be used to store and transmit data. Only one of the two buses, A or B, may be driven at a time.
To ensure the high-impedance state during power up or power down,
should be tied
to VCC through a pullup resistor; the minimum value of the
resistor is determined by the current-sinking capability of the
driver.
The SN74ABT646 is available in TI's shrink small-outline package (DB), which provides the same I/O pin count and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN54ABT646 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT646 is characterized for operation from -40°C to 85°C.
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技術資料
| 上位の文書 | タイプ | タイトル | フォーマットオプション | 最新の英語版をダウンロード | 日付 | |
|---|---|---|---|---|---|---|
| * | データシート | Octal Bus Transceivers And Registers With 3-State Outputs データシート (Rev. E) | 1994/07/01 |
設計と開発
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14-24-LOGIC-EVM — 14 ピンから 24 ピンの D、DB、DGV、DW、DYY、NS、PW の各パッケージに封止した各種ロジック製品向けの汎用評価基板
14-24-LOGIC-EVM 評価基板 (EVM) は、14 ピンから 24 ピンの D、DW、DB、NS、PW、DYY、DGV の各パッケージに封止した各種ロジック デバイスをサポートする設計を採用しています。
| パッケージ | ピン数 | CAD シンボル、フットプリント、および 3D モデル |
|---|---|---|
| TSSOP (PW) | 24 | Ultra Librarian |
| SOIC (DW) | 24 | Ultra Librarian |
| SSOP (DB) | 24 | Ultra Librarian |