ホーム ロジックと電圧変換 論理ゲート 複合ゲート
ホーム
ロジックと電圧変換
論理ゲート
複合ゲート

SN74AHC8541

アクティブ

SN74AHC8541

ご注文はこちら
データシート

SN74AHC8541

アクティブ
データシート ご注文はこちら

製品詳細

Technology family AHC Number of channels 8 Inputs per channel 1 IOL (max) (mA) 12 IOH (max) (mA) -12 Input type Standard CMOS Output type 3-State Features Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Data rate (max) (Mbps) 110 Rating Catalog Operating temperature range (°C) -40 to 85
Technology family AHC Number of channels 8 Inputs per channel 1 IOL (max) (mA) 12 IOH (max) (mA) -12 Input type Standard CMOS Output type 3-State Features Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Data rate (max) (Mbps) 110 Rating Catalog Operating temperature range (°C) -40 to 85
PDIP (N) 20 228.702 mm² (24.33 mm × 9.4 mm)
  • Operating Range of 2 V to 5.5 V VCC
  • 8-Bit Inverting/Non-Inverting Outputs
  • 20-Pin Thin Shrink Small-Outline Package
    [TSSOP (PW)] and 20-Pin Plastic Dual-In-Line
    Package [PDIP (N)]
  • Operating Range of 2 V to 5.5 V VCC
  • 8-Bit Inverting/Non-Inverting Outputs
  • 20-Pin Thin Shrink Small-Outline Package
    [TSSOP (PW)] and 20-Pin Plastic Dual-In-Line
    Package [PDIP (N)]

The SN74AHC8541 8-bit inverting/non-inverting buffers are ideal for driving bus lines or buffer memory address registers. These devices feature inputs and outputs on opposite sides of the package to facilitate printed circuit board layout.

All outputs are in the high-impedance state (disabled) when the output-enable (OE) input is high. When OE is low, the respective gate passes the data from the D input to its Y output.

The T/C input selects inverting or non-inverting data transfer. When the T/C input is high, it provides non-inverting buffers. When the T/C input is low, it provides inverting buffers when they are not in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74AHC8541 8-bit inverting/non-inverting buffers are ideal for driving bus lines or buffer memory address registers. These devices feature inputs and outputs on opposite sides of the package to facilitate printed circuit board layout.

All outputs are in the high-impedance state (disabled) when the output-enable (OE) input is high. When OE is low, the respective gate passes the data from the D input to its Y output.

The T/C input selects inverting or non-inverting data transfer. When the T/C input is high, it provides non-inverting buffers. When the T/C input is low, it provides inverting buffers when they are not in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
filter その他の 複合ゲート を検索
ダウンロード

技術資料

結果が見つかりませんでした。検索条件をクリアしてから、再度検索を試してください。
1 をすべて表示
上位の文書 タイプ タイトル フォーマットオプション 最新の英語版をダウンロード 日付
* データシート SN74AHC8541 8-BIT INVERTING/NONINVERTING SCHMITT-TRIGGER BUFFERS W/3-STATE OUT データシート 2009/04/08

購入と品質

サポートとトレーニング

TI E2E™ フォーラムでは、TI のエンジニアからの技術サポートを提供

投稿されたすべてのフォーラムトピック (英語) を表示

コンテンツは、TI 投稿者やコミュニティ投稿者によって「現状のまま」提供されるもので、TI による仕様の追加を意図するものではありません。使用条件をご確認ください。

TI 製品の品質、パッケージ、ご注文に関するお問い合わせは、TI サポートをご覧ください。​​​​​​​​​​​​​​