SN74GTLP21395

アクティブ

分割 LVTTL ポートとフィードバック・パス搭載、選択可能な極性、2 個の 1 ビット、LVTTL から GTLP への変換、調整可能なエッジ・レート・バス・トランシーバ

製品詳細

Technology family GTLP Applications GTL Rating Catalog Operating temperature range (°C) -40 to 85
Technology family GTLP Applications GTL Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (DW) 20 131.84 mm² 12.8 x 10.3 TSSOP (PW) 20 41.6 mm² 6.5 x 6.4
  • TI-OPC™ Circuitry Limits Ringing on Unevenly Loaded Backplanes
  • OEC™ Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference
  • Bidirectional Interface Between GTLP Signal Levels and LVTTL Logic Levels
  • Split LVTTL Port Provides a Feedback Path for Control and Diagnostics Monitoring
  • Y Outputs Have Equivalent 26- Series Resistors, So No External Resistors Are Required
  • LVTTL Interfaces Are 5-V Tolerant
  • High-Drive GTLP Outputs (100 mA)
  • LVTTL Outputs (–12 mA/12 mA)
  • Variable Edge-Rate Control (ERC) Input Selects GTLP Rise and Fall Times for Optimal Data-Transfer Rate and Signal Integrity in Distributed Loads
  • Ioff, Power-Up 3-State, and BIAS VCC Support Live Insertion
  • Polarity Control Selects True or Complementary Outputs
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

OEC and TI-OPC are trademarks of Texas Instruments.

  • TI-OPC™ Circuitry Limits Ringing on Unevenly Loaded Backplanes
  • OEC™ Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference
  • Bidirectional Interface Between GTLP Signal Levels and LVTTL Logic Levels
  • Split LVTTL Port Provides a Feedback Path for Control and Diagnostics Monitoring
  • Y Outputs Have Equivalent 26- Series Resistors, So No External Resistors Are Required
  • LVTTL Interfaces Are 5-V Tolerant
  • High-Drive GTLP Outputs (100 mA)
  • LVTTL Outputs (–12 mA/12 mA)
  • Variable Edge-Rate Control (ERC) Input Selects GTLP Rise and Fall Times for Optimal Data-Transfer Rate and Signal Integrity in Distributed Loads
  • Ioff, Power-Up 3-State, and BIAS VCC Support Live Insertion
  • Polarity Control Selects True or Complementary Outputs
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

OEC and TI-OPC are trademarks of Texas Instruments.

The SN74GTLP21395 is two 1-bit, high-drive, 3-wire bus transceivers that provide LVTTL-to-GTLP and GTLP-to-LVTTL signal-level translation for applications, such as primary and secondary clocks, that require individual output-enable and true/complement controls. The device allows for transparent and inverted transparent modes of data transfer with separate LVTTL input and LVTTL output pins, which provide a feedback path for control and diagnostics monitoring. The device provides a high-speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP signal levels and is designed especially to work with the Texas Instruments 3.3-V 1394 backplane physical-layer controller. High-speed (about three times faster than standard LVTTL or TTL) backplane operation is a direct result of GTLP reduced output swing (<1 V), reduced input threshold levels, improved differential input, OEC™ circuitry, and TI-OPC™ circuitry. Improved GTLP OEC and TI-OPC circuitry minimizes bus settling time, and have been designed and tested using several backplane models. The high drive allows incident-wave switching in heavily loaded backplanes, with equivalent load impedance down to 11 .

The Y outputs, which are designed to sink up to 12 mA, include equivalent 26- resistors to reduce overshoot and undershoot.

GTLP is the Texas Instruments derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The ac specification of the SN74GTLP21395 is given only at the preferred higher noise margin GTLP, but the user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTLP (VTT = 1.5 V and VREF = 1 V) signal levels. For information on using GTLP devices in FB+/BTL applications, refer to TI application reports, Texas Instruments GTLP Frequently Asked Questions, literature number SCEA019, and GTLP in BTL Applications, literature number SCEA017.

Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels, but are 5-V tolerant and are compatible with TTL or 5-V CMOS devices. VREF is the B-port differential input reference voltage.

This device is fully specified for live-insertion applications using Ioff , power-up 3-state, and BIAS VCC . The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The BIAS VCC circuitry precharges and preconditions the B-port input/output connections, preventing disturbance of active data on the backplane during card insertion or removal, and permits true live-insertion capability.

This GTLP device features TI-OPC circuitry, which actively limits the overshoot caused by improperly terminated backplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This improves signal integrity, which allows adequate noise margin to be maintained at higher frequencies.

High-drive GTLP backplane interface devices feature adjustable edge-rate control (ERC). Changing the ERC input voltage between low and high adjusts the B-port output rise and fall times.This allows the designer to optimize system data-transfer rate and signal integrity to the backplane load.

When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, the output-enable (OE\) input should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74GTLP21395 is two 1-bit, high-drive, 3-wire bus transceivers that provide LVTTL-to-GTLP and GTLP-to-LVTTL signal-level translation for applications, such as primary and secondary clocks, that require individual output-enable and true/complement controls. The device allows for transparent and inverted transparent modes of data transfer with separate LVTTL input and LVTTL output pins, which provide a feedback path for control and diagnostics monitoring. The device provides a high-speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP signal levels and is designed especially to work with the Texas Instruments 3.3-V 1394 backplane physical-layer controller. High-speed (about three times faster than standard LVTTL or TTL) backplane operation is a direct result of GTLP reduced output swing (<1 V), reduced input threshold levels, improved differential input, OEC™ circuitry, and TI-OPC™ circuitry. Improved GTLP OEC and TI-OPC circuitry minimizes bus settling time, and have been designed and tested using several backplane models. The high drive allows incident-wave switching in heavily loaded backplanes, with equivalent load impedance down to 11 .

The Y outputs, which are designed to sink up to 12 mA, include equivalent 26- resistors to reduce overshoot and undershoot.

GTLP is the Texas Instruments derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The ac specification of the SN74GTLP21395 is given only at the preferred higher noise margin GTLP, but the user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTLP (VTT = 1.5 V and VREF = 1 V) signal levels. For information on using GTLP devices in FB+/BTL applications, refer to TI application reports, Texas Instruments GTLP Frequently Asked Questions, literature number SCEA019, and GTLP in BTL Applications, literature number SCEA017.

Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels, but are 5-V tolerant and are compatible with TTL or 5-V CMOS devices. VREF is the B-port differential input reference voltage.

This device is fully specified for live-insertion applications using Ioff , power-up 3-state, and BIAS VCC . The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The BIAS VCC circuitry precharges and preconditions the B-port input/output connections, preventing disturbance of active data on the backplane during card insertion or removal, and permits true live-insertion capability.

This GTLP device features TI-OPC circuitry, which actively limits the overshoot caused by improperly terminated backplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This improves signal integrity, which allows adequate noise margin to be maintained at higher frequencies.

High-drive GTLP backplane interface devices feature adjustable edge-rate control (ERC). Changing the ERC input voltage between low and high adjusts the B-port output rise and fall times.This allows the designer to optimize system data-transfer rate and signal integrity to the backplane load.

When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, the output-enable (OE\) input should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

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技術資料

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種類 タイトル 最新の英語版をダウンロード 日付
* データシート Two 1-Bit LVTTL-to-GTLP Adjustable-Edge-Rate Bus Xcvrs w/ Split LVTTL Port, F/ba データシート (Rev. C) 2005年 12月 1日
アプリケーション・ノート Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators PDF | HTML 2024年 7月 12日
アプリケーション・ノート Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) PDF | HTML 2024年 7月 3日
セレクション・ガイド Voltage Translation Buying Guide (Rev. A) 2021年 4月 15日
セレクション・ガイド Logic Guide (Rev. AB) 2017年 6月 12日
アプリケーション・ノート Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
セレクション・ガイド ロジック・ガイド (Rev. AA 翻訳版) 最新英語版 (Rev.AB) 2014年 11月 6日
ユーザー・ガイド LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
アプリケーション・ノート Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
アプリケーション・ノート TI IBIS File Creation, Validation, and Distribution Processes 2002年 8月 29日
アプリケーション・ノート Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 2002年 5月 10日
アプリケーション・ノート Logic in Live-Insertion Applications With a Focus on GTLP 2002年 1月 14日
ユーザー・ガイド GTLP/GTL Logic High-Performance Backplane Drivers Data Book (Rev. A) 2001年 9月 15日
アプリケーション・ノート Achieving Maximum Speed on Parallel Buses With Gunning Transceiver Logic (GTLP) 2001年 4月 5日
セレクション・ガイド Advanced Bus Interface Logic Selection Guide 2001年 1月 9日
アプリケーション概要 Texas Instruments GTLP Frequently Asked Questions 2001年 1月 1日
アプリケーション・ノート Fast GTLP Backplanes With the GTLPH1655 (Rev. A) 2000年 9月 19日
その他の技術資料 High Level Brochure of Gunning Transceiver Logic Plus 2000年 1月 14日

設計および開発

その他のアイテムや必要なリソースを参照するには、以下のタイトルをクリックして詳細ページをご覧ください。

評価ボード

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ユーザー ガイド: PDF | HTML
シミュレーション・モデル

HSPICE MODEL OF SN74GTLP21395

SCEJ176.ZIP (99 KB) - HSpice Model
シミュレーション・モデル

SN74GTLP21395 IBIS Model

SCEM297.ZIP (34 KB) - IBIS Model
パッケージ ピン数 CAD シンボル、フットプリント、および 3D モデル
SOIC (DW) 20 Ultra Librarian
TSSOP (PW) 20 Ultra Librarian

購入と品質

記載されている情報:
  • RoHS
  • REACH
  • デバイスのマーキング
  • リード端子の仕上げ / ボールの原材料
  • MSL 定格 / ピーク リフロー
  • MTBF/FIT 推定値
  • 使用原材料
  • 認定試験結果
  • 継続的な信頼性モニタ試験結果
記載されている情報:
  • ファブの拠点
  • 組み立てを実施した拠点

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