SN74LVC574A-Q1

アクティブ

車載、3 ステート出力、1.65V ～ 3.6V、オクタルエッジトリガ D タイプフリップフロップ

ご注文はこちら

データシート

document-pdfAcrobat Octal Edge-Triggered D-Type Flip Flop With 3-State Outputs データシート (Rev. B) (英語)

SN74LVC574A-Q1

アクティブ

データシート

ご注文はこちら

製品詳細

Number of channels

8

Technology family

LVC

Input type

Standard CMOS

Output type

3-State

Clock frequency (max) (MHz)

100

IOL (max) (mA)

24

IOH (max) (mA)

-24

Supply current (max) (µA)

10

Features

Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Operating temperature range (°C)

-40 to 125

Rating

Automotive

Number of channels

8

Technology family

LVC

Input type

Standard CMOS

Output type

3-State

Clock frequency (max) (MHz)

100

IOL (max) (mA)

24

IOH (max) (mA)

-24

Supply current (max) (µA)

10

Features

Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Operating temperature range (°C)

-40 to 125

Rating

Automotive

TSSOP (PW)

20

41.6 mm² (6.5 mm × 6.4 mm)

SOIC (DW)

20

131.84 mm² (12.8 mm × 10.3 mm)

Qualified for Automotive Applications
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
Operates From 2 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max t_pd of 7 ns at 3.3 V
Typical V_OLP (Output Ground Bounce) < 0.8 V at V_CC = 3.3 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot) > 2 V at V_CC = 3.3 V, T_A = 25°C
Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V V_CC)
I_off Supports Partial-Power-Down Mode Operation

Qualified for Automotive Applications
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
Operates From 2 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max t_pd of 7 ns at 3.3 V
Typical V_OLP (Output Ground Bounce) < 0.8 V at V_CC = 3.3 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot) > 2 V at V_CC = 3.3 V, T_A = 25°C
Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V V_CC)
I_off Supports Partial-Power-Down Mode Operation

The SN74LVC574A octal edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V V_CC operation.

This device features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels at the data (D) inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of thIs device as a translator in a mixed 3.3-V/5-V system environment.