TMS320C6414T

アクティブ

McBSP 機能搭載、最大 1GHz、C64x 固定小数点 DSP

製品詳細

DSP type 1 C64x DSP (max) (MHz) 600, 720, 850, 1000 CPU 32-/64-bit Operating system DSP/BIOS Rating Catalog Operating temperature range (°C) -40 to 105
DSP type 1 C64x DSP (max) (MHz) 600, 720, 850, 1000 CPU 32-/64-bit Operating system DSP/BIOS Rating Catalog Operating temperature range (°C) -40 to 105
FCBGA (CLZ) 532 529 mm² 23 x 23 FCBGA (GLZ) 532 529 mm² 23 x 23
  • Highest-Performance Fixed-Point DSPs
    • 1.67-/1.39-/1.17-/1-ns Instruction Cycle
    • 600-/720-/850-MHz, 1-GHz Clock Rate
    • Eight 32-Bit Instructions/Cycle
    • Twenty-Eight Operations/Cycle
    • 4800, 5760, 6800, 8000 MIPS
    • Fully Software-Compatible With C62x™
    • C6414/15/16 Devices Pin-Compatible
    • Extended Temperature Devices Available
  • VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x™ DSP Core
    • Eight Highly Independent Functional Units With VelociTI.2™ Extensions:
      • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
      • Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
    • Non-Aligned Load-Store Architecture
    • 64 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
  • Instruction Set Features
    • Byte-Addressable (8-/16-/32-/64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • VelociTI.2™ Increased Orthogonality
  • VCP [C6416T Only]
    • Supports Over 833 7.95-Kbps AMR
    • Programmable Code Parameters
  • TCP [C6416T Only]
    • Supports up to 10 2-Mbps or 60 384-Kbps 3GPP (6 Iterations)
    • Programmable Turbo Code and Decoding Parameters
  • L1/L2 Memory Architecture
    • 128K-Bit (16K-Byte) L1P Program Cache(Direct Mapped)
    • 128K-Bit (16K-Byte) L1D Data Cache (2-Way Set-Associative)
    • 8M-Bit (1024K-Byte) L2 Unified Mapped RAM/Cache (Flexible Allocation)
  • Two External Memory Interfaces (EMIFs)
    • One 64-Bit (EMIFA), One 16-Bit (EMIFB)
    • Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO)
    • 1280M-Byte Total Addressable External Memory Space
  • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
  • Host-Port Interface (HPI)
    • User-Configurable Bus Width (32-/16-Bit)
  • 32-Bit/33-MHz, 3.3-V PCI Master/Slave Interface Conforms to PCI Specification 2.2 [C6415T/C6416T]
    • Three PCI Bus Address Registers:
          Prefetchable Memory
          Non-Prefetchable Memory I/O
    • Four-Wire Serial EEPROM Interface
    • PCI Interrupt Request Under DSP Program Control
    • DSP Interrupt Via PCI I/O Cycle
  • Three Multichannel Buffered Serial Ports
    • Direct Interface to T1/E1, MVIP, SCSA Framers
    • Up to 256 Channels Each
    • ST-Bus-Switching-, AC97-Compatible
    • Serial Peripheral Interface (SPI) Compatible (Motorola™)
  • Three 32-Bit General-Purpose Timers
  • UTOPIA [C6415T/C6416T]
    • UTOPIA Level 2 Slave ATM Controller
    • 8-Bit Transmit and Receive Operations up to 50 MHz per Direction
    • User-Defined Cell Format up to 64 Bytes
  • Sixteen General-Purpose I/O (GPIO) Pins
  • Flexible PLL Clock Generator
  • IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
  • 532-Pin Ball Grid Array (BGA) Package (GLZ and ZLZ Suffixes), 0.8-mm Ball Pitch
  • 0.09-µm/7-Level Cu Metal Process (CMOS)
  • 3.3-V I/Os, 1.1-V Internal (600 MHz)
  • 3.3-V I/Os, 1.2-V Internal (720/850 MHZ, 1 GHz)

C62x, VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
C62x, VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments.
Motorla is a registered trademark of the Motorola, Inc.

  • Highest-Performance Fixed-Point DSPs
    • 1.67-/1.39-/1.17-/1-ns Instruction Cycle
    • 600-/720-/850-MHz, 1-GHz Clock Rate
    • Eight 32-Bit Instructions/Cycle
    • Twenty-Eight Operations/Cycle
    • 4800, 5760, 6800, 8000 MIPS
    • Fully Software-Compatible With C62x™
    • C6414/15/16 Devices Pin-Compatible
    • Extended Temperature Devices Available
  • VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x™ DSP Core
    • Eight Highly Independent Functional Units With VelociTI.2™ Extensions:
      • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
      • Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
    • Non-Aligned Load-Store Architecture
    • 64 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
  • Instruction Set Features
    • Byte-Addressable (8-/16-/32-/64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • VelociTI.2™ Increased Orthogonality
  • VCP [C6416T Only]
    • Supports Over 833 7.95-Kbps AMR
    • Programmable Code Parameters
  • TCP [C6416T Only]
    • Supports up to 10 2-Mbps or 60 384-Kbps 3GPP (6 Iterations)
    • Programmable Turbo Code and Decoding Parameters
  • L1/L2 Memory Architecture
    • 128K-Bit (16K-Byte) L1P Program Cache(Direct Mapped)
    • 128K-Bit (16K-Byte) L1D Data Cache (2-Way Set-Associative)
    • 8M-Bit (1024K-Byte) L2 Unified Mapped RAM/Cache (Flexible Allocation)
  • Two External Memory Interfaces (EMIFs)
    • One 64-Bit (EMIFA), One 16-Bit (EMIFB)
    • Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO)
    • 1280M-Byte Total Addressable External Memory Space
  • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
  • Host-Port Interface (HPI)
    • User-Configurable Bus Width (32-/16-Bit)
  • 32-Bit/33-MHz, 3.3-V PCI Master/Slave Interface Conforms to PCI Specification 2.2 [C6415T/C6416T]
    • Three PCI Bus Address Registers:
          Prefetchable Memory
          Non-Prefetchable Memory I/O
    • Four-Wire Serial EEPROM Interface
    • PCI Interrupt Request Under DSP Program Control
    • DSP Interrupt Via PCI I/O Cycle
  • Three Multichannel Buffered Serial Ports
    • Direct Interface to T1/E1, MVIP, SCSA Framers
    • Up to 256 Channels Each
    • ST-Bus-Switching-, AC97-Compatible
    • Serial Peripheral Interface (SPI) Compatible (Motorola™)
  • Three 32-Bit General-Purpose Timers
  • UTOPIA [C6415T/C6416T]
    • UTOPIA Level 2 Slave ATM Controller
    • 8-Bit Transmit and Receive Operations up to 50 MHz per Direction
    • User-Defined Cell Format up to 64 Bytes
  • Sixteen General-Purpose I/O (GPIO) Pins
  • Flexible PLL Clock Generator
  • IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
  • 532-Pin Ball Grid Array (BGA) Package (GLZ and ZLZ Suffixes), 0.8-mm Ball Pitch
  • 0.09-µm/7-Level Cu Metal Process (CMOS)
  • 3.3-V I/Os, 1.1-V Internal (600 MHz)
  • 3.3-V I/Os, 1.2-V Internal (720/850 MHZ, 1 GHz)

C62x, VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
C62x, VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments.
Motorla is a registered trademark of the Motorola, Inc.

The TMS320C64x™ DSPs (including the TMS320C6414T, TMS320C6415T, and TMS320C6416T devices) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The TMS320C64x™ (C64x™) device is based on the second-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture (VelociTI.2™) developed by Texas Instruments (TI), making these DSPs an excellent choice for wireless infrastructure applications. The C64x™ is a code-compatible member of the C6000™ DSP platform.

With performance of up to 8000 million instructions per second (MIPS) at a clock rate of 1 GHz, the C64x devices offer cost-effective solutions to high-performance DSP programming challenges. The C64x™ DSPs possess the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x. DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs)— with VelociTI.2™ extensions. The VelociTI.2™ extensions in the eight functional units include new instructions to accelerate the performance in key applications and extend the parallelism of the VelociTI™ architecture. The C64x can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 4000 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 8000 MMACS. The C64x DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000™ DSP platform devices.

The C6416T device has two high-performance embedded coprocessors [Viterbi Decoder Coprocessor (VCP) and Turbo Decoder Coprocessor (TCP)] that significantly speed up channel-decoding operations on-chip. The VCP operating at CPU clock divided-by-4 can decode over 833 7.95-Kbps adaptive multi-rate (AMR) [K = 9, R = 1/3] voice channels. The VCP supports constraint lengths K = 5, 6, 7, 8, and 9, rates R = 1/2, 1/3, and 1/4, and flexible polynomials, while generating hard decisions or soft decisions. The TCP operating at CPU clock divided-by-2 can decode up to sixty 384-Kbps or ten 2-Mbps turbo encoded channels (assuming 6 iterations). The TCP implements the max*log-map algorithm and is designed to support all polynomials and rates required by Third-Generation Partnership Projects (3GPP and 3GPP2), with fully programmable frame length and turbo interleaver. Decoding parameters such as the number of iterations and stopping criteria are also programmable. Communications between the VCP/TCP and the CPU are carried out through the EDMA controller.

The C64x uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 8-Mbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory or combinations of cache (up to 256K bytes) and mapped memory. The peripheral set includes three multichannel buffered serial ports (McBSPs); an 8-bit Universal Test and Operations PHY Interface for Asynchronous Transfer Mode (ATM) Slave [UTOPIA Slave] port [C6415T/C6416T only]; three 32-bit general-purpose timers; a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a peripheral component interconnect (PCI) [C6415T/C6416T only]; a general-purpose input/output port (GPIO) with 16 GPIO pins; and two glueless external memory interfaces (64-bit EMIFA and 16-bit EMIFB), both of which are capable of interfacing to synchronous and asynchronous memories and peripherals.

The C64x has a complete set of development tools which includes: an advanced C compiler with C64x-specific enhancements, an assembly optimizer to simplify programming and scheduling, and a Windows. debugger interface for visibility into source code execution.

TMS320C6000, C64x, and C6000 are trademarks of Texas Instruments.
Windows is a registered trademark of the Microsoft Corporation.
Other trademarks are the property of their respective owners.
Throughout the remainder of this document, the TMS320C6414T, TMS320C6415T, and TMS320C6416T shall be referred to as TMS320C64x or C64x where generic, and where specific, their individual full device part numbers will be used or abbreviated as C6414T, C6415T, or C6416T.
These C64x™ devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix "A" in front of a signal name indicates it is an EMIFA signal whereas a prefix "B" in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted from the signal name.

The TMS320C64x™ DSPs (including the TMS320C6414T, TMS320C6415T, and TMS320C6416T devices) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The TMS320C64x™ (C64x™) device is based on the second-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture (VelociTI.2™) developed by Texas Instruments (TI), making these DSPs an excellent choice for wireless infrastructure applications. The C64x™ is a code-compatible member of the C6000™ DSP platform.

With performance of up to 8000 million instructions per second (MIPS) at a clock rate of 1 GHz, the C64x devices offer cost-effective solutions to high-performance DSP programming challenges. The C64x™ DSPs possess the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x. DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs)— with VelociTI.2™ extensions. The VelociTI.2™ extensions in the eight functional units include new instructions to accelerate the performance in key applications and extend the parallelism of the VelociTI™ architecture. The C64x can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 4000 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 8000 MMACS. The C64x DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000™ DSP platform devices.

The C6416T device has two high-performance embedded coprocessors [Viterbi Decoder Coprocessor (VCP) and Turbo Decoder Coprocessor (TCP)] that significantly speed up channel-decoding operations on-chip. The VCP operating at CPU clock divided-by-4 can decode over 833 7.95-Kbps adaptive multi-rate (AMR) [K = 9, R = 1/3] voice channels. The VCP supports constraint lengths K = 5, 6, 7, 8, and 9, rates R = 1/2, 1/3, and 1/4, and flexible polynomials, while generating hard decisions or soft decisions. The TCP operating at CPU clock divided-by-2 can decode up to sixty 384-Kbps or ten 2-Mbps turbo encoded channels (assuming 6 iterations). The TCP implements the max*log-map algorithm and is designed to support all polynomials and rates required by Third-Generation Partnership Projects (3GPP and 3GPP2), with fully programmable frame length and turbo interleaver. Decoding parameters such as the number of iterations and stopping criteria are also programmable. Communications between the VCP/TCP and the CPU are carried out through the EDMA controller.

The C64x uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 8-Mbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory or combinations of cache (up to 256K bytes) and mapped memory. The peripheral set includes three multichannel buffered serial ports (McBSPs); an 8-bit Universal Test and Operations PHY Interface for Asynchronous Transfer Mode (ATM) Slave [UTOPIA Slave] port [C6415T/C6416T only]; three 32-bit general-purpose timers; a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a peripheral component interconnect (PCI) [C6415T/C6416T only]; a general-purpose input/output port (GPIO) with 16 GPIO pins; and two glueless external memory interfaces (64-bit EMIFA and 16-bit EMIFB), both of which are capable of interfacing to synchronous and asynchronous memories and peripherals.

The C64x has a complete set of development tools which includes: an advanced C compiler with C64x-specific enhancements, an assembly optimizer to simplify programming and scheduling, and a Windows. debugger interface for visibility into source code execution.

TMS320C6000, C64x, and C6000 are trademarks of Texas Instruments.
Windows is a registered trademark of the Microsoft Corporation.
Other trademarks are the property of their respective owners.
Throughout the remainder of this document, the TMS320C6414T, TMS320C6415T, and TMS320C6416T shall be referred to as TMS320C64x or C64x where generic, and where specific, their individual full device part numbers will be used or abbreviated as C6414T, C6415T, or C6416T.
These C64x™ devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix "A" in front of a signal name indicates it is an EMIFA signal whereas a prefix "B" in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted from the signal name.

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種類 タイトル 最新の英語版をダウンロード 日付
* データシート TMS320C6414T, TMS320C6415T, TMS320C6416T Fixed-Point Digital Signal Processors データシート (Rev. M) 2009年 4月 6日
* エラッタ TMS320C6414T/C6415T/C6416T DSPs Silicon Errata (Silicon Revision 2.0, 1.0) (Rev. J) 2012年 7月 26日
アプリケーション・ノート How to Migrate CCS 3.x Projects to the Latest CCS (Rev. A) PDF | HTML 2021年 5月 19日
ユーザー・ガイド Emulation and Trace Headers Technical Reference Manual (Rev. I) 2012年 8月 9日
アプリケーション・ノート Introduction to TMS320C6000 DSP Optimization 2011年 10月 6日
製品概要 TMS320C6000 高性能 DSP シリーズ プロダクト・ブリテン (Rev. B 翻訳版) 2008年 11月 17日
アプリケーション・ノート Migrating from TMS320C6416/15/14 to TMS320C6416T/15T/14T (Rev. B) 2008年 2月 22日
アプリケーション・ノート TMS320C6414T/15T/16T Power Consumption Summary (Rev. A) 2008年 2月 18日
製品概要 TMS320C6000 DSP TCP/IP Stack Software (Rev. C) 2007年 4月 4日
アプリケーション・ノート TMS320C6000 EDMA IO Scheduling and Performance 2004年 3月 5日
アプリケーション・ノート TMS320C64x DSP Host Port Interface (HPI) Performance 2003年 10月 24日

設計および開発

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デバッグ・プローブ

TMDSEMU560V2STM-U — XDS560™ ソフトウェア v2 システム・トレース USB デバッグ・プローブ

XDS560v2 は、XDS560™ ファミリのデバッグ・プローブの中で最高の性能を達成し、従来の JTAG 規格 (IEEE1149.1) と cJTAG (IEEE1149.7) の両方をサポートしています。シリアル・ワイヤ・デバッグ (SWD) をサポートしていないことに注意してください。

すべての XDS デバッグ・プローブは、組み込みトレース・バッファ (ETB) を搭載しているすべての ARM プロセッサと DSP プロセッサで、コア・トレースとシステム・トレースをサポートしています。ピン経由でコア・トレースを実行する場合、XDS560v2 PRO TRACE が必要です。

(...)

デバッグ・プローブ

TMDSEMU560V2STM-UE — Spectrum Digital XDS560v2 システム・トレース USB およびイーサネット

The XDS560v2 System Trace is the first model of the XDS560v2 family of high-performance debug probes (emulators) for TI processors. The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).

The (...)

ドライバまたはライブラリ

SPRC090 Download TMS320C6000 Chip Support Library

The Chip Support Library (CSL) provides an application programming interface (API) used for configuring and controlling the DSP on-chip peripherals for ease of use, compatibility between various C6000 devices and hardware abstraction. This will shorten development time by providing standardization (...)
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サポート対象の製品とハードウェア

製品
デジタル信号プロセッサ (DSP)
TMS320C6412 C64x 固定小数点 DSP - 最大 720MHz、McBSP と McASP と I2cC とイーサネット搭載 TMS320C6414 C64x 固定小数点 DSP:最大 720MHz、McBSP 搭載 TMS320C6414T McBSP 機能搭載、最大 1GHz、C64x 固定小数点 DSP TMS320C6415 C64x 固定小数点 DSP - 最大 720MHz、McBSP と PCI 搭載 TMS320C6415T C64x 固定小数点 DSP - 最大 850MHz、McBSP と PCI 搭載 TMS320C6416 C64x 固定小数点 DSP - 最大 720MHz、McBSP と PCI と VCP/TCP 搭載 TMS320C6416T C64x 固定小数点 DSP - 最大 850MHz、McBSP と PCI と VCP/TCP 搭載 TMS320C6701 C67x 浮動小数点 DSP - 最大 167MHz、McBSP 搭載 TMS320DM640 ビデオ / 画像処理向け固定小数点デジタル シグナル プロセッサ TMS320DM641 ビデオ / 画像処理向け固定小数点デジタル シグナル プロセッサ TMS320DM642 ビデオ / 画像処理向け固定小数点デジタル シグナル プロセッサ TMS320DM642Q ビデオ / 画像処理向け、固定小数点デジタル信号プロセッサ
ドライバまたはライブラリ

SPRC122 C62x/C64x Fast Run-Time Support Library

The C62x/64x FastRTS Library is an optimized, floating-point function library for C programmers using either TMS320C62x or TMS320C64x devices. These routines are typically used in computationally intensive real-time applications where optimal execution speed is critical. By replacing the current (...)

サポート対象の製品とハードウェア

サポート対象の製品とハードウェア

製品
デジタル信号プロセッサ (DSP)
SM320C6201-EP エンハンスド製品、C6201 固定小数点 DSP SM320C6455-EP エンハンスド製品、C6455 の固定小数点 DSP SMJ320C6201B ミリタリー、固定小数点デジタル・シグナル・プロセッサ SMJ320C6203 ミリタリー・グレード C62x 固定小数点 DSP - セラミック・パッケージ TMS320C6202B C62x 固定小数点 DSP - 最大 300MHz、384KB TMS320C6203B C62x 固定小数点 DSP - 最大 300MHz、896KB TMS320C6204 固定小数点デジタル・シグナル・プロセッサ TMS320C6205 固定小数点デジタル・シグナル・プロセッサ TMS320C6211B C62x 固定小数点 DSP - 最大 167MHz TMS320C6412 C64x 固定小数点 DSP - 最大 720MHz、McBSP と McASP と I2cC とイーサネット搭載 TMS320C6414 C64x 固定小数点 DSP:最大 720MHz、McBSP 搭載 TMS320C6414T McBSP 機能搭載、最大 1GHz、C64x 固定小数点 DSP TMS320C6415 C64x 固定小数点 DSP - 最大 720MHz、McBSP と PCI 搭載 TMS320C6415T C64x 固定小数点 DSP - 最大 850MHz、McBSP と PCI 搭載 TMS320C6416 C64x 固定小数点 DSP - 最大 720MHz、McBSP と PCI と VCP/TCP 搭載 TMS320C6416T C64x 固定小数点 DSP - 最大 850MHz、McBSP と PCI と VCP/TCP 搭載 TMS320C6421 C64x+ 固定小数点 DSP - 最大 600MHz、8 ビット EMIFA (非同期 EMIF) と 16 ビット DDR2 SDRAM 搭載 TMS320C6421Q C64x+ 固定小数点 DSP - 最大 600MHz、8 ビット EMIFA (非同期 EMIF) と 16 ビット DDR2 搭載 TMS320C6424 C64x+ 固定小数点 DSP - 最大 600MHz、16/8 ビット EMIFA (非同期 EMIF) と 32/16 ビット DDR2 SDRAM 搭載 TMS320C6424Q C64x+ 固定小数点 DSP - 最大 600MHz、16/8 ビット EMIFA (非同期 EMIF) と 32/16 ビット DDR2 搭載 TMS320C6452 C64x+ 固定小数点 DSP:最大 900MHz、1Gbps イーサネット搭載 TMS320C6454 C64x+ 固定小数点 DSP - 最大 1GHz、64 ビット EMIFA (非同期 EMIF) と 32/16 ビット DDR2 と 1Gbps イーサネット搭載 TMS320C6455 C64x+ 固定小数点 DSP、最大 1.2GHz、64 ビット EMIFA、32 および 16 ビット DDR2、1Gbps イーサネット TMS320C6457 通信インフラ デジタル シグナル プロセッサ TMS320C6474 マルチコア デジタル シグナル プロセッサ TMS320DM640 ビデオ / 画像処理向け固定小数点デジタル シグナル プロセッサ TMS320DM641 ビデオ / 画像処理向け固定小数点デジタル シグナル プロセッサ TMS320DM642 ビデオ / 画像処理向け固定小数点デジタル シグナル プロセッサ TMS320DM642Q ビデオ / 画像処理向け、固定小数点デジタル信号プロセッサ TMS320DM6431 デジタル メディア プロセッサ TMS320DM6431Q 最大 2400MIPS、300MHz クロック・レート、デジタル・メディア・プロセッサ TMS320DM6433 デジタル メディア プロセッサ TMS320DM6435 デジタル メディア プロセッサ TMS320DM6435Q 最大 4800MIPS、600MHz クロック レート、1 x McASP、1 x McBSP 搭載、デジタル メディア プロセッサ TMS320DM6437 デジタル メディア プロセッサ TMS320DM6437Q 最大 4800MIPS、600MHz クロック レート、1 x McASP、2 x McBSP 搭載、デジタル メディア プロセッサ TMS320DM6441 DaVinci デジタル メディア システムオンチップ TMS320DM6443 DaVinci デジタル メディア システムオンチップ TMS320DM6446 DaVinci デジタル メディア システムオンチップ
ドライバまたはライブラリ

SPRC264 — C64x+IMGLIB

C5000/6000 Image Processing Library (IMGLIB) is an optimized image/video processing function library for C programmers. It includes C-callable general-purpose image/video processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
ユーザー ガイド: PDF
ドライバまたはライブラリ

SPRC265 — C64x+DSPLIB

TMS320C6000 Digital Signal Processor Library (DSPLIB) is a platform-optimized DSP function library for C programmers. It includes C-callable, general-purpose signal-processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
ユーザー ガイド: PDF
ドライバまたはライブラリ

TELECOMLIB — テレコムおよびメディア向けライブラリ - FAXLIB、VoLIB および AEC/AER、TMS320C64x+ および TMS320C55x プロセッサ用

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)
IDE (統合開発環境)、コンパイラ、またはデバッガ

CCSTUDIO Code Composer Studio 統合開発環境(IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It comprises a suite of tools used to develop and debug embedded applications.  Code Composer Studio is available for download across Windows®, Linux® and macOS® desktops. It can also (...)

サポート対象の製品とハードウェア

サポート対象の製品とハードウェア

こちらの設計リソースは、このカテゴリに属する製品の大半をサポートしています。

サポート状況を確認するには、製品の詳細ページをご覧ください。

開始 ダウンロードオプション
シミュレーション・モデル

C6414T, C6415T, C6416T GLZ BSDL Model Version 1.1

SPRM146.ZIP (14 KB) - BSDL Model
シミュレーション・モデル

C6414T, C6415T, C6416T GLZ BSDL Model, Version 2.0

SPRM206.ZIP (14 KB) - BSDL Model
シミュレーション・モデル

C6414T, C6415T, C6416T GLZ IBIS Model

SPRM147.ZIP (78 KB) - IBIS Model
パッケージ ピン数 CAD シンボル、フットプリント、および 3D モデル
FCBGA (CLZ) 532 Ultra Librarian
FCBGA (GLZ) 532 Ultra Librarian

購入と品質

記載されている情報:
  • RoHS
  • REACH
  • デバイスのマーキング
  • リード端子の仕上げ / ボールの原材料
  • MSL 定格 / ピーク リフロー
  • MTBF/FIT 推定値
  • 使用原材料
  • 認定試験結果
  • 継続的な信頼性モニタ試験結果
記載されている情報:
  • ファブの拠点
  • 組み立てを実施した拠点

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