ADC12DL500

활성

12비트, 듀얼 500MSPS 또는 싱글 1GSPS 아날로그-디지털 컨버터(LVDS 인터페이스)

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데이터 시트

document-pdfAcrobat ADC12DLx500 0.5, 1.5, 2.5GSPS Dual-Channel or 1, 3, 5GSPS Single-Channel,12-Bit Analog-to-Digital Converters (ADC) With LVDS Interface datasheet (영어) PDF | HTML

ADC12DL500

활성

데이터 시트

지금 주문하기

제품 상세 정보

Sample rate (max) (Msps)

500, 1000

Resolution (Bits)

12

Number of input channels

1, 2

Interface type

DDR LVDS, Parallel LVDS

Analog input BW (MHz)

8000

Features

Ultra High Speed

Rating

Catalog

Peak-to-peak input voltage range (V)

0.8

Power consumption (typ) (mW)

2500

Architecture

Folding Interpolating

SNR (dB)

56.8

ENOB (Bits)

9

SFDR (dB)

69

Operating temperature range (°C)

-40 to 85

Input buffer

Yes

Sample rate (max) (Msps)

500, 1000

Resolution (Bits)

12

Number of input channels

1, 2

Interface type

DDR LVDS, Parallel LVDS

Analog input BW (MHz)

8000

Features

Ultra High Speed

Rating

Catalog

Peak-to-peak input voltage range (V)

0.8

Power consumption (typ) (mW)

2500

Architecture

Folding Interpolating

SNR (dB)

56.8

ENOB (Bits)

9

SFDR (dB)

69

Operating temperature range (°C)

-40 to 85

Input buffer

Yes

FCBGA (ACF)

256

289 mm² (0 mm × 0 mm)

ADC core:
- 12-Bit resolution
- Up to 1GSPS, 3GSPS, 5GSPS in single-channel mode
- Up to 500MSPS, 1.5GSPS, 2.5GSPS in dual-channel mode
Internal dither for low-magnitude, high-order harmonics
Low-latency LVDS interface:
- Total latency: < 10ns
- Up to 48 data pairs at 1.6Gbps
- Four DDR data clocks
- Strobe signals simplify synchronization
Noise floor (no input, VFS = 1VPP-DIFF):
- Dual-channel mode: -143.5, -148, -149.8dBFS/Hz
- Single-channel mode: -146.2, -150.3, -152.2dBFS/Hz
Buffered analog inputs with VCMI of 0V:
- Analog input bandwidth (–3dB): 8GHz
- Full-scale input voltage (VFS, default): 0.8VPP
Noiseless aperture delay (TAD) adjustment:
- Precise sampling control: 19fs step
- Simplifies synchronization and interleaving
- Temperature and voltage invariant delays
Easy-to-use synchronization features:
- Automatic SYSREF timing calibration
- Timestamp for sample marking
Power consumption: 2.6, 2.8, 3W

ADC core:
- 12-Bit resolution
- Up to 1GSPS, 3GSPS, 5GSPS in single-channel mode
- Up to 500MSPS, 1.5GSPS, 2.5GSPS in dual-channel mode
Internal dither for low-magnitude, high-order harmonics
Low-latency LVDS interface:
- Total latency: < 10ns
- Up to 48 data pairs at 1.6Gbps
- Four DDR data clocks
- Strobe signals simplify synchronization
Noise floor (no input, VFS = 1VPP-DIFF):
- Dual-channel mode: -143.5, -148, -149.8dBFS/Hz
- Single-channel mode: -146.2, -150.3, -152.2dBFS/Hz
Buffered analog inputs with VCMI of 0V:
- Analog input bandwidth (–3dB): 8GHz
- Full-scale input voltage (VFS, default): 0.8VPP
Noiseless aperture delay (TAD) adjustment:
- Precise sampling control: 19fs step
- Simplifies synchronization and interleaving
- Temperature and voltage invariant delays
Easy-to-use synchronization features:
- Automatic SYSREF timing calibration
- Timestamp for sample marking
Power consumption: 2.6, 2.8, 3W

The ADC12DL500, ADC12DL1500 and ADC12DL2500 are a family of analog-to-digital converters (ADC) that can sample up to 500MSPS, 1.5GSPS, and 2.5GSPS in dual-channel mode and up to 1GSPS, 3GSPS, and 5GSPS in single-channel mode. Programmable tradeoffs in channel count (dual-channel mode) and sample rate (single-channel mode) allow development of flexible hardware that meets the needs of both high-channel count or wide instantaneous signal bandwidth applications.

The devices uses a low-latency, low-voltage differential signaling (LVDS) interface for latency sensitive applications or when the simplicity of LVDS is preferred. The interface uses up to 48 data pairs, four double data rate (DDR) clocks, and four strobe signals arranged in four 12-bit data buses. The interface supports signaling rates of up to 1.6Gbps. Strobe signals simplify synchronization across buses and between multiple devices. The strobe is generated internally and can be reset at a deterministic time by the SYSREF input. Multi-device synchronization is further eased by innovative synchronization features such as noiseless aperture delay (TAD) adjustment and SYSREF windowing.

The ADC12DL500, ADC12DL1500 and ADC12DL2500 are a family of analog-to-digital converters (ADC) that can sample up to 500MSPS, 1.5GSPS, and 2.5GSPS in dual-channel mode and up to 1GSPS, 3GSPS, and 5GSPS in single-channel mode. Programmable tradeoffs in channel count (dual-channel mode) and sample rate (single-channel mode) allow development of flexible hardware that meets the needs of both high-channel count or wide instantaneous signal bandwidth applications.

The devices uses a low-latency, low-voltage differential signaling (LVDS) interface for latency sensitive applications or when the simplicity of LVDS is preferred. The interface uses up to 48 data pairs, four double data rate (DDR) clocks, and four strobe signals arranged in four 12-bit data buses. The interface supports signaling rates of up to 1.6Gbps. Strobe signals simplify synchronization across buses and between multiple devices. The strobe is generated internally and can be reset at a deterministic time by the SYSREF input. Multi-device synchronization is further eased by innovative synchronization features such as noiseless aperture delay (TAD) adjustment and SYSREF windowing.

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기타 고속 ADC(≥10 MSPS) 찾기

다운로드 스크립트와 함께 비디오 보기 비디오

기술 자료

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2개 모두 보기

상위 문서	유형	직함	형식 옵션	최신 영어 버전 다운로드	날짜
*	데이터 시트	ADC12DLx500 0.5, 1.5, 2.5GSPS Dual-Channel or 1, 3, 5GSPS Single-Channel,12-Bit Analog-to-Digital Converters (ADC) With LVDS Interface datasheet	PDF \| HTML		2024. 1. 31
	기술 문서	So, what are S-parameters anyway?	PDF \| HTML		2019. 5. 23

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

평가 보드

ADC12DL2500EVM — ADC12DL2500 평가 모듈

ADC12DL2500 EVM(평가 모듈)은 고속 ADC(아날로그-디지털 컨버터)인 ADC12DL2500 제품군을 평가하기 위해 설계되었습니다. EVM에는 LVDS 인터페이스를 지원하는 12비트, 듀얼 채널 2.5GSPS 또는 싱글 채널 5GSPS ADC인 ADC12DL2500이 장착되어 있어 제품군의 모든 샘플 레이트 장치를 평가할 수 있습니다.

사용 설명서: PDF | HTML

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