ADC3669
- 16-bit, dual channel 250 and 500MSPS ADC
- Noise spectral density: -160.4dBFS/Hz
- Thermal Noise: 76.4dBFS
- Single core (non-interleaved) ADC architecture
- Aperture jitter: 75fs
- Buffered analog inputs
- Programmable 100Ω and 200Ω termination
- Input fullscale: 2VPP
- Full power input bandwidth (-3dB): 1.4GHz
- Spectral performance (fIN = 70MHz, -1dBFS):
- SNR: 75.6dBFS
- SFDR HD2,3: 80dBc
- SFDR worst spur: 94dBFS
- INL: ±2 LSB (typical)
- DNL: ±0.5 LSB (typical)
- Digital down-converters (DDCs)
- Up to four independent DDCs
- Complex and real decimation
- Decimation: /2, /4 to /32768 decimation
- 48-bit NCO phase coherent frequency hopping
- DDR/Serial LVDS interface
- 16-bit Parallel DDR LVDS for DDC bypass
- Serial LVDS for decimation
- 32-bit output option for high decimation
- Power consumption: 300mW/channel (500MSPS)
The ADC3668 and ADC3669 (ADC366x) are a 16-bit, 250MSPS and 500MSPS, dual channel analog to digital converters (ADC). The devices are designed for high signal-to-noise ratio (SNR) and deliver a noise spectral density of −160dBFS/Hz (500MSPS).
The ADC366x includes an optional quad band digital down-converter (DDC) supporting wide band decimation by 2 to narrow band decimation by 32768. The DDC uses a 48-bit NCO which supports phase coherent and phase continuous frequency hopping.
The ADC366x is outfitted with a flexible LVDS interface. In decimation bypass mode, the device uses a 16-bit wide parallel DDR LVDS interface. When using decimation, the output data is transmitted using a serial LVDS interface reducing the number of lanes needed as decimation increases. For high decimation ratios, the output resolution can be increased to 32-bit.
The power efficient ADC architecture consumes 300mW/ch at 500MSPS and provides power scaling with lower sampling rates (250mW/ch at 250MSPS).
기술 자료
| 상위 문서 | 유형 | 직함 | 형식 옵션 | 최신 영어 버전 다운로드 | 날짜 |
|---|---|---|---|---|---|
| * | 데이터 시트 | ADC3668, ADC3669 Dual-Channel, 16-Bit 250MSPS and 500MSPS Analog-to-Digital Converter (ADC) datasheet (Rev. B) | PDF | HTML | 2025. 6. 5 | |
| 애플리케이션 노트 | Optimizing IFF Transponder Turnaround Time Using Ultra-Low Latency ADCs | PDF | HTML | 2026. 7. 16 | ||
| 아날로그 디자인 학술지 | 협대역 정합 고속 RF ADC에 대한 새로 운 방식 | PDF | HTML | Download English Version | 2025. 12. 1 | |
| 아날로그 디자인 학술지 | 고속 컨버터의 나이퀴스트 홀 주변 샘플 링 | PDF | HTML | Download English Version | 2025. 5. 23 | |
| 애플리케이션 노트 | Comparing Active vs. Passive High-Speed/RF A/D Converter Front Ends | PDF | HTML | 2025. 3. 28 | ||
| 애플리케이션 노트 | Evaluating High-Speed, RF ADC Converter Front-end Architectures | PDF | HTML | 2025. 3. 26 | ||
| 애플리케이션 노트 | Improving MSPS ADC’s SFDR While Relaxing AAF Requirements and Using Integrated DDC Features | PDF | HTML | 2025. 2. 18 | ||
| 애플리케이션 노트 | The Fine Art of Passive Matching a High-Speed A/D Converter Analog Input Frontend | PDF | HTML | 2024. 12. 13 | ||
| 아날로그 디자인 학술지 | 고속 ADC 아날로그 입력 프론트 엔드를 패시브 매칭하는 기술 | PDF | HTML | Download English Version | 2024. 10. 9 |
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
ADC3669EVM — ADC3669 평가 모듈
ADC3669-NOISE-ANALYSIS-CALC — Noise analysis calculation tool (SNR/SFDR) for ADC3669 with amplifier input.
ADC-DAC-TO-VREF-SELECT-DESIGN-TOOL — The ADC-TO-VREF-SELECT tool enables the pairing of TI ADCs, DACs, and series voltage references.
| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| VQFNP (RTD) | 64 | Ultra Librarian |
주문 및 품질
권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.